From: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@linux.intel.com>
To: Terry Bowman <terry.bowman@amd.com>,
PradeepVineshReddy.Kodamati@amd.com, dave@stgolabs.net,
jonathan.cameron@huawei.com, dave.jiang@intel.com,
alison.schofield@intel.com, vishal.l.verma@intel.com,
ira.weiny@intel.com, dan.j.williams@intel.com,
bhelgaas@google.com, bp@alien8.de, ming.li@zohomail.com,
shiju.jose@huawei.com, dan.carpenter@linaro.org,
Smita.KoralahalliChannabasappa@amd.com,
kobayashi.da-06@fujitsu.com, yanfei.xu@intel.com,
rrichter@amd.com, peterz@infradead.org, colyli@suse.de,
uaisheng.ye@intel.com, fabio.m.de.francesco@linux.intel.com,
ilpo.jarvinen@linux.intel.com, yazen.ghannam@amd.com,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org
Subject: Re: [PATCH v9 15/16] CXL/PCI: Enable CXL protocol errors during CXL Port probe
Date: Thu, 5 Jun 2025 17:51:53 -0700 [thread overview]
Message-ID: <6b47a383-3e57-44f7-a3c6-45af88c04897@linux.intel.com> (raw)
In-Reply-To: <20250603172239.159260-16-terry.bowman@amd.com>
On 6/3/25 10:22 AM, Terry Bowman wrote:
> CXL protocol errors are not enabled for all CXL devices after boot. These
> must be enabled inorder to process CXL protocol errors.
>
> Export the AER service driver's pci_aer_unmask_internal_errors().
>
> Introduce cxl_unmask_prot_interrupts() to call pci_aer_unmask_internal_errors().
> pci_aer_unmask_internal_errors() expects the pdev->aer_cap is initialized.
> But, dev->aer_cap is not initialized for CXL Upstream Switch Ports and CXL
> Downstream Switch Ports. Initialize the dev->aer_cap if necessary. Enable AER
> correctable internal errors and uncorrectable internal errors for all CXL
> devices.
>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> drivers/cxl/port.c | 29 +++++++++++++++++++++++++++--
> drivers/pci/pcie/aer.c | 3 ++-
> include/linux/aer.h | 1 +
> 3 files changed, 30 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index 0f7c4010ba58..3687848ae772 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
> @@ -3,6 +3,7 @@
> #include <linux/device.h>
> #include <linux/module.h>
> #include <linux/slab.h>
> +#include <linux/pci.h>
>
> #include "cxlmem.h"
> #include "cxlpci.h"
> @@ -60,6 +61,21 @@ static int discover_region(struct device *dev, void *unused)
>
> #ifdef CONFIG_PCIEAER_CXL
>
> +static void cxl_unmask_prot_interrupts(struct device *dev)
> +{
> + struct pci_dev *pdev __free(pci_dev_put) =
> + pci_dev_get(to_pci_dev(dev));
> +
> + if (!pdev->aer_cap) {
> + pdev->aer_cap = pci_find_ext_capability(pdev,
> + PCI_EXT_CAP_ID_ERR);
> + if (!pdev->aer_cap)
> + return;
> + }
> +
> + pci_aer_unmask_internal_errors(pdev);
> +}
> +
> static void cxl_dport_map_rch_aer(struct cxl_dport *dport)
> {
> resource_size_t aer_phys;
> @@ -118,8 +134,12 @@ static void cxl_uport_init_ras_reporting(struct cxl_port *port,
>
> map->host = host;
> if (cxl_map_component_regs(map, &port->uport_regs,
> - BIT(CXL_CM_CAP_CAP_ID_RAS)))
> + BIT(CXL_CM_CAP_CAP_ID_RAS))) {
> dev_dbg(&port->dev, "Failed to map RAS capability\n");
> + return;
> + }
> +
> + cxl_unmask_prot_interrupts(port->uport_dev);
> }
>
> /**
> @@ -144,9 +164,12 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host)
> }
>
> if (cxl_map_component_regs(&dport->reg_map, &dport->regs.component,
> - BIT(CXL_CM_CAP_CAP_ID_RAS)))
> + BIT(CXL_CM_CAP_CAP_ID_RAS))) {
> dev_dbg(dport->dport_dev, "Failed to map RAS capability\n");
> + return;
> + }
>
> + cxl_unmask_prot_interrupts(dport->dport_dev);
> }
> EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL");
>
> @@ -177,6 +200,8 @@ static void cxl_endpoint_port_init_ras(struct cxl_port *port)
> }
>
> cxl_dport_init_ras_reporting(dport, &cxlmd->dev);
> +
> + cxl_unmask_prot_interrupts(cxlmd->cxlds->dev);
> }
>
> #else
> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
> index 5efe5a718960..2d202ad1453a 100644
> --- a/drivers/pci/pcie/aer.c
> +++ b/drivers/pci/pcie/aer.c
> @@ -964,7 +964,7 @@ static bool find_source_device(struct pci_dev *parent,
> * Note: AER must be enabled and supported by the device which must be
> * checked in advance, e.g. with pcie_aer_is_native().
> */
> -static void pci_aer_unmask_internal_errors(struct pci_dev *dev)
> +void pci_aer_unmask_internal_errors(struct pci_dev *dev)
> {
> int aer = dev->aer_cap;
> u32 mask;
> @@ -977,6 +977,7 @@ static void pci_aer_unmask_internal_errors(struct pci_dev *dev)
> mask &= ~PCI_ERR_COR_INTERNAL;
> pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask);
> }
> +EXPORT_SYMBOL_NS_GPL(pci_aer_unmask_internal_errors, "CXL");
>
> static bool is_cxl_mem_dev(struct pci_dev *dev)
> {
> diff --git a/include/linux/aer.h b/include/linux/aer.h
> index c9a18eca16f8..74600e75705f 100644
> --- a/include/linux/aer.h
> +++ b/include/linux/aer.h
> @@ -107,5 +107,6 @@ void pci_print_aer(struct pci_dev *dev, int aer_severity,
> int cper_severity_to_aer(int cper_severity);
> void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
> int severity, struct aer_capability_regs *aer_regs);
> +void pci_aer_unmask_internal_errors(struct pci_dev *dev);
> #endif //_AER_H_
>
--
Sathyanarayanan Kuppuswamy
Linux Kernel Developer
next prev parent reply other threads:[~2025-06-06 0:51 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-03 17:22 [PATCH v9 00/16] Enable CXL PCIe port protocol error handling and logging Terry Bowman
2025-06-03 17:22 ` [PATCH v9 01/16] PCI/CXL: Add pcie_is_cxl() Terry Bowman
2025-06-04 19:06 ` Sathyanarayanan Kuppuswamy
2025-06-04 19:18 ` Bowman, Terry
2025-06-05 23:24 ` Dave Jiang
2025-06-03 17:22 ` [PATCH v9 02/16] PCI/AER: Report CXL or PCIe bus error type in trace logging Terry Bowman
2025-06-03 22:02 ` Sathyanarayanan Kuppuswamy
2025-06-04 14:32 ` Bowman, Terry
2025-06-04 19:24 ` Sathyanarayanan Kuppuswamy
2025-06-04 21:30 ` Bowman, Terry
2025-06-05 23:28 ` Dave Jiang
2025-06-03 17:22 ` [PATCH v9 03/16] CXL/AER: Introduce kfifo for forwarding CXL errors Terry Bowman
2025-06-04 6:01 ` Dan Carpenter
2025-06-04 14:37 ` Bowman, Terry
2025-06-04 17:24 ` Dan Carpenter
2025-06-04 19:21 ` Bowman, Terry
2025-06-04 22:50 ` Sathyanarayanan Kuppuswamy
2025-06-05 14:04 ` Bowman, Terry
2025-06-06 0:27 ` Dave Jiang
2025-06-06 14:27 ` Bowman, Terry
2025-06-06 14:36 ` Dave Jiang
2025-06-12 11:04 ` Jonathan Cameron
2025-06-12 14:29 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 04/16] PCI/AER: Dequeue forwarded CXL error Terry Bowman
2025-06-04 6:05 ` Dan Carpenter
2025-06-04 14:38 ` Bowman, Terry
2025-06-04 23:58 ` Sathyanarayanan Kuppuswamy
2025-06-06 15:57 ` Dave Jiang
2025-06-06 18:14 ` Bowman, Terry
2025-06-06 22:43 ` Dave Jiang
2025-06-09 19:57 ` Bowman, Terry
2025-06-09 20:34 ` Dave Jiang
2025-06-12 11:17 ` Jonathan Cameron
2025-06-06 21:08 ` Bowman, Terry
2025-06-06 23:15 ` Bowman, Terry
2025-06-09 20:17 ` Dave Jiang
2025-06-10 4:15 ` Lukas Wunner
2025-06-10 18:07 ` Bowman, Terry
2025-06-10 21:20 ` Bowman, Terry
2025-06-11 4:38 ` Lukas Wunner
2025-06-17 16:08 ` Dave Jiang
2025-06-17 18:20 ` Robert Richter
2025-06-12 11:36 ` Jonathan Cameron
2025-06-12 18:35 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 05/16] CXL/PCI: Introduce CXL uncorrectable protocol error recovery Terry Bowman
2025-06-05 15:14 ` Sathyanarayanan Kuppuswamy
2025-06-05 16:01 ` Bowman, Terry
2025-06-06 16:45 ` Dave Jiang
2025-06-06 18:16 ` Bowman, Terry
2025-06-12 16:06 ` Jonathan Cameron
2025-06-12 16:29 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 06/16] cxl/pci: Move RAS initialization to cxl_port driver Terry Bowman
2025-06-06 17:04 ` Dave Jiang
2025-06-06 18:17 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 07/16] cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers Terry Bowman
2025-06-03 17:22 ` [PATCH v9 08/16] cxl/pci: Update RAS handler interfaces to also support CXL Ports Terry Bowman
2025-06-05 16:42 ` Sathyanarayanan Kuppuswamy
2025-06-03 17:22 ` [PATCH v9 09/16] cxl/pci: Log message if RAS registers are unmapped Terry Bowman
2025-06-05 16:42 ` Sathyanarayanan Kuppuswamy
2025-06-06 17:27 ` Dave Jiang
2025-06-03 17:22 ` [PATCH v9 10/16] cxl/pci: Unify CXL trace logging for CXL Endpoints and CXL Ports Terry Bowman
2025-06-05 16:49 ` Sathyanarayanan Kuppuswamy
2025-06-06 9:08 ` Shiju Jose
2025-06-06 14:41 ` Bowman, Terry
2025-06-06 15:24 ` Bowman, Terry
2025-06-12 16:25 ` Jonathan Cameron
2025-06-03 17:22 ` [PATCH v9 11/16] cxl/pci: Update __cxl_handle_cor_ras() to return early if no RAS errors Terry Bowman
2025-06-05 18:37 ` Sathyanarayanan Kuppuswamy
2025-06-06 20:30 ` Dave Jiang
2025-06-06 20:55 ` Bowman, Terry
2025-06-06 22:38 ` Dave Jiang
2025-06-12 16:46 ` Jonathan Cameron
2025-06-16 20:30 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 12/16] cxl/pci: Introduce CXL Endpoint protocol error handlers Terry Bowman
2025-06-06 0:22 ` Sathyanarayanan Kuppuswamy
2025-06-12 16:55 ` Jonathan Cameron
2025-06-03 17:22 ` [PATCH v9 13/16] cxl/pci: Introduce CXL Port " Terry Bowman
2025-06-06 0:50 ` Sathyanarayanan Kuppuswamy
2025-06-12 17:14 ` Jonathan Cameron
2025-06-16 22:17 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 14/16] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Terry Bowman
2025-06-06 0:50 ` Sathyanarayanan Kuppuswamy
2025-06-12 17:16 ` Jonathan Cameron
2025-06-03 17:22 ` [PATCH v9 15/16] CXL/PCI: Enable CXL protocol errors during CXL Port probe Terry Bowman
2025-06-06 0:51 ` Sathyanarayanan Kuppuswamy [this message]
2025-06-03 17:22 ` [PATCH v9 16/16] CXL/PCI: Disable CXL protocol error interrupts during CXL Port cleanup Terry Bowman
2025-06-06 0:52 ` Sathyanarayanan Kuppuswamy
2025-06-06 13:51 ` Bowman, Terry
2025-06-06 22:59 ` Dave Jiang
2025-06-12 17:19 ` Jonathan Cameron
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