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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id n10-20020a170906700a00b006efdb748e8dsm8274074ejj.88.2022.04.28.05.07.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Apr 2022 05:07:59 -0700 (PDT) Message-ID: <6bd8eb4e-81eb-7e87-155b-f48b487e16ae@linaro.org> Date: Thu, 28 Apr 2022 14:07:58 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH v4 6/7] dt-bindings: pci/qcom,pcie: support additional MSI interrupts Content-Language: en-US To: Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Rob Herring , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org References: <20220428115934.3414641-1-dmitry.baryshkov@linaro.org> <20220428115934.3414641-7-dmitry.baryshkov@linaro.org> From: Krzysztof Kozlowski In-Reply-To: <20220428115934.3414641-7-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 28/04/2022 13:59, Dmitry Baryshkov wrote: > On Qualcomm platforms each group of 32 MSI vectors is routed to the > separate GIC interrupt. Document mapping of additional interrupts. > > Signed-off-by: Dmitry Baryshkov > --- > .../devicetree/bindings/pci/qcom,pcie.yaml | 51 ++++++++++++++++++- > 1 file changed, 50 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index 0b69b12b849e..a8f99bca389e 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -43,11 +43,20 @@ properties: > maxItems: 5 > > interrupts: > - maxItems: 1 > + minItems: 1 > + maxItems: 8 > > interrupt-names: > + minItems: 1 > items: > - const: msi > + - const: msi2 > + - const: msi3 > + - const: msi4 > + - const: msi5 > + - const: msi6 > + - const: msi7 > + - const: msi8 > > # Common definitions for clocks, clock-names and reset. > # Platform constraints are described later. > @@ -623,6 +632,46 @@ allOf: > - resets > - reset-names > > + # On newer chipsets support either 1 or 8 msi interrupts > + # On older chipsets it's always 1 msi interrupt > + - if: > + properties: > + compatibles: > + contains: > + enum: > + - qcom,pcie-msm8996 > + - qcom,pcie-sc7280 > + - qcom,pcie-sc8180x > + - qcom,pcie-sdm845 > + - qcom,pcie-sm8150 > + - qcom,pcie-sm8250 > + - qcom,pcie-sm8450-pcie0 > + - qcom,pcie-sm8450-pcie1 > + then: > + oneOf: > + - properties: > + interrupts: > + minItems: 1 minItems should not be needed here and in places below, because it is equal to maxItems. > + maxItems: 1 > + interrupt-names: > + minItems: 1 > + maxItems: 1 > + - properties: > + interrupts: > + minItems: 8 > + maxItems: 8 > + interrupt-names: > + minItems: 8 > + maxItems: 8 > + else: > + properties: > + interrupts: > + minItems: 1 > + maxItems: 1 > + interrupt-names: > + minItems: 1 > + maxItems: 1 > + > unevaluatedProperties: false > > examples: Best regards, Krzysztof