From: Patrice CHOTARD <patrice.chotard@foss.st.com>
To: Alain Volmat <avolmat@me.com>, Rob Herring <robh+dt@kernel.org>,
<linux-pci@vger.kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Subject: Re: [PATCH RESEND v2 4/5] ARM: dts: sti: add the PCIe controller node within stih407-family
Date: Mon, 24 Jan 2022 13:47:40 +0100 [thread overview]
Message-ID: <6d45806f-d8f0-dabd-ae65-a820c1880ed4@foss.st.com> (raw)
In-Reply-To: <20220103074731.3651-5-avolmat@me.com>
Hi Alain
On 1/3/22 08:47, Alain Volmat wrote:
> Add the pcie1 entry within stih407-family dtsi.
>
> Signed-off-by: Alain Volmat <avolmat@me.com>
> ---
> arch/arm/boot/dts/stih407-family.dtsi | 40 +++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
> index 21f3347a91d6..fe4ea2d5b583 100644
> --- a/arch/arm/boot/dts/stih407-family.dtsi
> +++ b/arch/arm/boot/dts/stih407-family.dtsi
> @@ -631,6 +631,46 @@ spifsm: spifsm@9022000{
> status = "disabled";
> };
>
> + pcie1: pcie@9b10000 {
> + compatible = "st,stih407-pcie";
> + device_type = "pci";
> + reg = <0x09b10000 0x00001000>, /* cntrl registers */
> + <0x3fff0000 0x00010000>, /* config space */
> + <0x40000000 0xc0000000>; /* lmi mem window */
> +
> + reg-names = "dbi",
> + "config",
> + "mem-window";
> +
> + st,syscfg = <&syscfg_core 0xdc 0xe4>;
> +
> + #interrupt-cells = <1>;
> + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &intc GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &intc GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + /* non-prefetchable and prefetchable */
> + ranges = <0x82000000 0 0x30000000 0x30000000 0 0x05550000>,
> + <0xc2000000 0 0x35550000 0x35550000 0 0x0AAA0000>;
> + bus-range = <0x00 0xff>;
> +
> + resets = <&softreset STIH407_PCIE1_SOFTRESET>,
> + <&powerdown STIH407_PCIE1_POWERDOWN>;
> +
> + reset-names = "softreset", "powerdown";
> +
> + phys = <&phy_port1 PHY_TYPE_PCIE>;
> + phy-names = "pcie";
> +
> + status = "disabled";
> + };
> +
> sata0: sata@9b20000 {
> compatible = "st,ahci";
> reg = <0x9b20000 0x1000>;
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Thanks
Patrice
next prev parent reply other threads:[~2022-01-24 12:48 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-03 7:47 [PATCH RESEND v2 0/5] Introduction of PCIe support on STi platform Alain Volmat
2022-01-03 7:47 ` [PATCH RESEND v2 1/5] dt-bindings: pci: st-pcie: PCIe controller found on STi platforms Alain Volmat
2022-01-24 20:06 ` Bjorn Helgaas
2022-01-03 7:47 ` [PATCH RESEND v2 2/5] pci: dwc: pcie-st: Add PCIe driver for " Alain Volmat
2022-01-24 12:45 ` Patrice CHOTARD
2022-01-24 20:15 ` Bjorn Helgaas
2022-01-03 7:47 ` [PATCH RESEND v2 3/5] MAINTAINERS: add entry for ST STI PCIE driver Alain Volmat
2022-01-24 12:46 ` Patrice CHOTARD
2022-01-03 7:47 ` [PATCH RESEND v2 4/5] ARM: dts: sti: add the PCIe controller node within stih407-family Alain Volmat
2022-01-24 12:47 ` Patrice CHOTARD [this message]
2022-01-03 7:47 ` [PATCH RESEND v2 5/5] ARM: dts: sti: enable PCIe on the stih418-b2264 board Alain Volmat
2022-01-24 12:48 ` Patrice CHOTARD
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