From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Elad Nachman <enachman@marvell.com>,
thomas.petazzoni@bootlin.com, bhelgaas@google.com,
lpieralisi@kernel.org, robh@kernel.org, kw@linux.com,
krzysztof.kozlowski+dt@linaro.org, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 4/7] dt-bindings: PCI: dwc: add DMA, region mask bits
Date: Thu, 23 Feb 2023 19:12:17 +0100 [thread overview]
Message-ID: <6dfde695-16d5-57ac-fbdd-b86ec91322a9@linaro.org> (raw)
In-Reply-To: <20230223180531.15148-5-enachman@marvell.com>
On 23/02/2023 19:05, Elad Nachman wrote:
> From: Elad Nachman <enachman@marvell.com>
>
> Add properties to support configurable DMA mask bits
> and region mask bits.
> configurable DMA mask bits is needed for Marvell AC5/AC5X SOCs which
> have their physical DDR memory start at address 0x2_0000_0000.
> Configurable region mask bits is needed for the Marvell Armada
> 7020/7040/8040 SOCs when the DT file places the PCIe window above the
> 4GB region.
> The Synopsis Designware PCIe IP in these SOCs is too old to specify the
> highest memory location supported by the PCIe, but practically supports
> such locations. Allow these locations to be specified in the DT file.
This formatting is so bad it makes difficult to read. Make these proper
sentences with proper wrapping.
> First DT property is called num-dmamask,
> and can range between 33 and 64.
Wrong mapping and we see it in the code. No need to code it again in
commit msg. Especially that you already said it in the first sentence.
> Second DT property is called num-regionmask,
> and can range between 33 and 64.
>
> Signed-off-by: Elad Nachman <enachman@marvell.com>
> ---
> .../devicetree/bindings/pci/snps,dw-pcie-common.yaml | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> index d87e13496834..a1b06ff19ca7 100644
> --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> @@ -261,6 +261,16 @@ properties:
>
> dma-coherent: true
>
> + num-dmamask:
> + description: |
> + number of dma mask bits to use, if different than default 32
minimum: 33 (from commit msg)
default: 32... which does not make now sense...
> + maximum: 64
> +
> + num-regionmask:
> + description: |
> + number of region limit mask bits to use, if different than default 32
> + maximum: 64
> +
> additionalProperties: true
>
> ...
Best regards,
Krzysztof
next prev parent reply other threads:[~2023-02-23 18:12 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-23 18:05 [PATCH v3 0/7] PCI: dwc: Add support for Marvell AC5 SoC Elad Nachman
2023-02-23 18:05 ` [PATCH v3 1/7] dt-bindings: PCI: armada8k: Add compatible string for " Elad Nachman
2023-02-23 18:05 ` [PATCH v3 2/7] PCI: armada8k: Add AC5 SoC support Elad Nachman
2023-02-23 18:05 ` [PATCH v3 3/7] PCI: armada8k: Add MSI support for AC5 SoC Elad Nachman
2023-02-23 18:05 ` [PATCH v3 4/7] dt-bindings: PCI: dwc: add DMA, region mask bits Elad Nachman
2023-02-23 18:12 ` Krzysztof Kozlowski [this message]
2023-02-27 18:55 ` Rob Herring
2023-02-23 18:05 ` [PATCH v3 5/7] PCI: dwc: support AC5 Legacy PCIe interrupts Elad Nachman
2023-02-23 19:48 ` Bjorn Helgaas
2023-02-23 18:05 ` [PATCH v3 6/7] PCI: dwc: Introduce Configurable DMA mask Elad Nachman
2023-02-23 18:14 ` Krzysztof Kozlowski
2023-02-23 18:05 ` [PATCH v3 7/7] PCI: dwc: Introduce region limit from DT Elad Nachman
2023-02-23 18:16 ` Krzysztof Kozlowski
2023-02-23 19:42 ` [PATCH v3 0/7] PCI: dwc: Add support for Marvell AC5 SoC Bjorn Helgaas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=6dfde695-16d5-57ac-fbdd-b86ec91322a9@linaro.org \
--to=krzysztof.kozlowski@linaro.org \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=enachman@marvell.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kw@linux.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=robh@kernel.org \
--cc=thomas.petazzoni@bootlin.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).