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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA1OSBTYWx0ZWRfX/dkJj4454bgL XDmZySLVa4rlPenyxLPaU3zqqJJbkywMlgBx8taZGfDBI3B399PNvo3PeMJ8RpBnamYMy6jU/Qb c+0secs2XEPJZUYgF30ocUESpyosXoUi87YlUkhg781ztPwn9C2J+2JjSDPmnUkUY9lOO7S1lXn 7gw5qxpETWG1Bx8fy04gXjtMYSiF6RhnE5zz4gGR+iduXkMDK9ggleVpG0oL/MMdyjo9T/UuAv2 0VJCklNrjdYkj8g1IvAhJf8+gTwOaLZ5llPGNjw3nI6jXuMBLiBEwalAfG+qGRUOY6A5p9xcRv6 zguW/GvMRQJiddYBhpXzt0I5V3DahvezidL1QT26fUoBGzzgpHsrj39AspeQJXPRQ1qTMozHyqU ag74onwIJGboAh6zylui95FGq6V9bk+eB/H9CAzb967G7fdHoZ9O0RPRz1BojtWx3c5VfGy//fy vOSSItR9+r9jgMsK8ww== X-Proofpoint-GUID: Hq8qyslew-dJdZd0N-BcYfi1Vluy9e9x X-Proofpoint-ORIG-GUID: Hq8qyslew-dJdZd0N-BcYfi1Vluy9e9x X-Authority-Analysis: v=2.4 cv=KYbfcAYD c=1 sm=1 tr=0 ts=6948e9c7 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=s8YR1HE3AAAA:8 a=a8IibEu9Vj4pwpCw0c0A:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 a=jGH_LyMDp9YhSvY-UuyI:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 phishscore=0 malwarescore=0 spamscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220059 On 12/22/2025 12:12 PM, Niklas Cassel wrote: > This reverts commit ba4a2e2317b9faeca9193ed6d3193ddc3cf2aba3. > > While this fake hotplugging was a nice idea, it has shown that this feature > does not handle PCIe switches correctly: > pci_bus 0004:43: busn_res: can not insert [bus 43-41] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci_bus 0004:43: busn_res: [bus 43-41] end is updated to 43 > pci_bus 0004:43: busn_res: can not insert [bus 43] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci 0004:42:00.0: devices behind bridge are unusable because [bus 43] cannot be assigned for them > pci_bus 0004:44: busn_res: can not insert [bus 44-41] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci_bus 0004:44: busn_res: [bus 44-41] end is updated to 44 > pci_bus 0004:44: busn_res: can not insert [bus 44] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci 0004:42:02.0: devices behind bridge are unusable because [bus 44] cannot be assigned for them > pci_bus 0004:45: busn_res: can not insert [bus 45-41] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci_bus 0004:45: busn_res: [bus 45-41] end is updated to 45 > pci_bus 0004:45: busn_res: can not insert [bus 45] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci 0004:42:06.0: devices behind bridge are unusable because [bus 45] cannot be assigned for them > pci_bus 0004:46: busn_res: can not insert [bus 46-41] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci_bus 0004:46: busn_res: [bus 46-41] end is updated to 46 > pci_bus 0004:46: busn_res: can not insert [bus 46] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci 0004:42:0e.0: devices behind bridge are unusable because [bus 46] cannot be assigned for them > pci_bus 0004:42: busn_res: [bus 42-41] end is updated to 46 > pci_bus 0004:42: busn_res: can not insert [bus 42-46] under [bus 41] (conflicts with (null) [bus 41]) > pci 0004:41:00.0: devices behind bridge are unusable because [bus 42-46] cannot be assigned for them > pcieport 0004:40:00.0: bridge has subordinate 41 but max busn 46 > > During the initial scan, PCI core doesn't see the switch and since the Root > Port is not hot plug capable, the secondary bus number gets assigned as the > subordinate bus number. This means, the PCI core assumes that only one bus > will appear behind the Root Port since the Root Port is not hot plug > capable. > > This works perfectly fine for PCIe endpoints connected to the Root Port, > since they don't extend the bus. However, if a PCIe switch is connected, > then there is a problem when the downstream busses starts showing up and > the PCI core doesn't extend the subordinate bus number after initial scan > during boot. > > The long term plan is to migrate this driver to the pwrctrl framework, > once it adds proper support for powering up and enumerating PCIe switches. > > Cc: stable@vger.kernel.org > Suggested-by: Manivannan Sadhasivam > Acked-by: Shawn Lin > Tested-by: Shawn Lin > Signed-off-by: Niklas Cassel > --- > drivers/pci/controller/dwc/pcie-qcom.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index e87ec6779d44..c5fcb87972e9 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -136,7 +136,6 @@ > > /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ > #define PARF_INT_ALL_LINK_UP BIT(13) > -#define PARF_INT_MSI_DEV_0_7 GENMASK(30, 23) > > /* PARF_NO_SNOOP_OVERRIDE register fields */ > #define WR_NO_SNOOP_OVERRIDE_EN BIT(1) > @@ -1982,8 +1981,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) > goto err_host_deinit; > } > > - writel_relaxed(PARF_INT_ALL_LINK_UP | PARF_INT_MSI_DEV_0_7, > - pcie->parf + PARF_INT_ALL_MASK); MSI's needs to be enabled irrespective of this series as part of global IRQ otherwise MSI's will not be triggered in few platforms. Mani, exclude this patch while applying. - Krishna Chaitanya > + writel_relaxed(PARF_INT_ALL_LINK_UP, pcie->parf + PARF_INT_ALL_MASK); > } > > qcom_pcie_icc_opp_update(pcie);