* [PATCH v4 0/4] Add Qualcomm SA8255p based firmware managed PCIe root complex
@ 2025-05-22 0:14 Mayank Rana
2025-05-22 0:14 ` [PATCH v4 1/4] PCI: dwc: Export dwc MSI controller related APIs Mayank Rana
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: Mayank Rana @ 2025-05-22 0:14 UTC (permalink / raw)
To: linux-pci, lpieralisi, kw, robh, bhelgaas, andersson,
manivannan.sadhasivam, krzysztof.kozlowski+dt, conor+dt,
devicetree
Cc: linux-arm-msm, quic_ramkri, quic_nkela, quic_shazhuss,
quic_msarkar, quic_nitegupt, Mayank Rana
Based on received feedback, this patch series adds support with existing
Linux qcom-pcie.c driver to get PCIe host root complex functionality on
Qualcomm SA8255P auto platform.
1. Interface to allow requesting firmware to manage system resources and
performing PCIe Link up (devicetree binding in terms of power domain and
runtime PM APIs is used in driver)
2. SA8255P is using Synopsys Designware PCIe controller which supports MSI
controller. Using existing MSI controller based functionality by exporting
important pcie dwc core driver based MSI APIs, and using those from
pcie-qcom.c driver.
Below architecture is used on Qualcomm SA8255P auto platform to get ECAM
compliant PCIe controller based functionality. Here firmware VM based PCIe
driver takes care of resource management and performing PCIe link related
handling (D0 and D3cold). Linux pcie-qcom.c driver uses power domain to
request firmware VM to perform these operations using SCMI interface.
--------------------
┌────────────────────────┐
│ │
┌──────────────────────┐ │ SHARED MEMORY │ ┌──────────────────────────┐
│ Firmware VM │ │ │ │ Linux VM │
│ ┌─────────┐ │ │ │ │ ┌────────────────┐ │
│ │ Drivers │ ┌──────┐ │ │ │ │ │ PCIE Qcom │ │
│ │ PCIE PHY◄─┤ │ │ │ ┌────────────────┐ │ │ │ driver │ │
│ │ │ │ SCMI │ │ │ │ │ │ │ │ │ │
│ │PCIE CTL │ │ │ ├─────────┼───► PCIE ◄───┼─────┐ │ └──┬──────────▲──┘ │
│ │ ├─►Server│ │ │ │ SHMEM │ │ │ │ │ │ │
│ │Clk, Vreg│ │ │ │ │ │ │ │ │ │ ┌──▼──────────┴──┐ │
│ │GPIO,GDSC│ └─▲──┬─┘ │ │ └────────────────┘ │ └──────┼────┤PCIE SCMI Inst │ │
│ └─────────┘ │ │ │ │ │ │ └──▲──────────┬──┘ │
│ │ │ │ │ │ │ │ │ │
└───────────────┼──┼───┘ │ │ └───────┼──────────┼───────┘
│ │ │ │ │ │
│ │ └────────────────────────┘ │ │
│ │ │ │
│ │ │ │
│ │ │ │
│ │ │IRQ │HVC
IRQ │ │HVC │ │
│ │ │ │
│ │ │ │
│ │ │ │
┌─────────────────┴──▼───────────────────────────────────────────────────────────┴──────────▼──────────────┐
│ │
│ │
│ HYPERVISOR │
│ │
│ │
│ │
└──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
┌─────────────┐ ┌─────────────┐ ┌──────────┐ ┌───────────┐ ┌─────────────┐ ┌────────────┐
│ │ │ │ │ │ │ │ │ PCIE │ │ PCIE │
│ CLOCK │ │ REGULATOR │ │ GPIO │ │ GDSC │ │ PHY │ │ controller │
└─────────────┘ └─────────────┘ └──────────┘ └───────────┘ └─────────────┘ └────────────┘
-----------------
Changes in v4:
- Addressed provided review comments from reviewers
Link to v3: https://lore.kernel.org/lkml/20241106221341.2218416-1-quic_mrana@quicinc.com/
Changes in v3:
- Drop usage of PCIE host generic driver usage, and splitting of MSI functionality
- Modified existing pcie-qcom.c driver to add support for getting ECAM compliant and firmware managed
PCIe root complex functionality
Link to v2: https://lore.kernel.org/linux-arm-kernel/925d1eca-975f-4eec-bdf8-ca07a892361a@quicinc.com/T/
Changes in v2:
- Drop new PCIe Qcom ECAM driver, and use existing PCIe designware based MSI functionality
- Add power domain based functionality within existing ECAM driver
Link to v1: https://lore.kernel.org/all/d10199df-5fb3-407b-b404-a0a4d067341f@quicinc.com/T/
Tested:
- Validated NVME functionality with PCIe1 on SA8255P-RIDE platform
Mayank Rana (4):
PCI: dwc: Export dwc MSI controller related APIs
PCI: host-generic: Rename and export gen_pci_init() API to allow ECAM
creation
dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root
complex
PCI: qcom: Add Qualcomm SA8255p based PCIe root complex functionality
.../bindings/pci/qcom,pcie-sa8255p.yaml | 103 ++++++++++++++++
drivers/pci/controller/dwc/Kconfig | 1 +
.../pci/controller/dwc/pcie-designware-host.c | 38 +++---
drivers/pci/controller/dwc/pcie-designware.h | 14 +++
drivers/pci/controller/dwc/pcie-qcom.c | 114 ++++++++++++++++--
drivers/pci/controller/pci-host-common.c | 5 +-
include/linux/pci-ecam.h | 2 +
7 files changed, 248 insertions(+), 29 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml
--
2.25.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v4 1/4] PCI: dwc: Export dwc MSI controller related APIs
2025-05-22 0:14 [PATCH v4 0/4] Add Qualcomm SA8255p based firmware managed PCIe root complex Mayank Rana
@ 2025-05-22 0:14 ` Mayank Rana
2025-05-22 0:14 ` [PATCH v4 2/4] PCI: host-generic: Rename and export gen_pci_init() to allow ECAM creation Mayank Rana
` (3 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Mayank Rana @ 2025-05-22 0:14 UTC (permalink / raw)
To: linux-pci, lpieralisi, kw, robh, bhelgaas, andersson,
manivannan.sadhasivam, krzysztof.kozlowski+dt, conor+dt,
devicetree
Cc: linux-arm-msm, quic_ramkri, quic_nkela, quic_shazhuss,
quic_msarkar, quic_nitegupt, Mayank Rana
Export dw_pcie_msi_host_init(), dw_pcie_msi_init(), and dw_pcie_free_msi()
APIs to allow dwc PCIe controller based MSI functionality from ECAM pcie
driver. Move MSI IRQ related initialization code into dw_pcie_msi_init()
as this code must be executed before dw_pcie_msi_init() API can be used
with ECAM driver.
Signed-off-by: Mayank Rana <mayank.rana@oss.qualcomm.com>
---
.../pci/controller/dwc/pcie-designware-host.c | 38 ++++++++++---------
drivers/pci/controller/dwc/pcie-designware.h | 14 +++++++
2 files changed, 34 insertions(+), 18 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index d2291c3ceb8b..4e382cfc7c80 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -250,7 +250,7 @@ int dw_pcie_allocate_domains(struct dw_pcie_rp *pp)
return 0;
}
-static void dw_pcie_free_msi(struct dw_pcie_rp *pp)
+void dw_pcie_free_msi(struct dw_pcie_rp *pp)
{
u32 ctrl;
@@ -263,19 +263,34 @@ static void dw_pcie_free_msi(struct dw_pcie_rp *pp)
irq_domain_remove(pp->msi_domain);
irq_domain_remove(pp->irq_domain);
}
+EXPORT_SYMBOL_GPL(dw_pcie_free_msi);
-static void dw_pcie_msi_init(struct dw_pcie_rp *pp)
+void dw_pcie_msi_init(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
u64 msi_target = (u64)pp->msi_data;
+ u32 ctrl, num_ctrls;
if (!pci_msi_enabled() || !pp->has_msi_ctrl)
return;
+ num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
+
+ /* Initialize IRQ Status array */
+ for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
+ dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
+ (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
+ pp->irq_mask[ctrl]);
+ dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
+ (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
+ ~0);
+ }
+
/* Program the msi_data */
dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target));
dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
}
+EXPORT_SYMBOL_GPL(dw_pcie_msi_init);
static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp)
{
@@ -317,7 +332,7 @@ static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp)
return 0;
}
-static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
+int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct device *dev = pci->dev;
@@ -391,6 +406,7 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
return 0;
}
+EXPORT_SYMBOL_GPL(dw_pcie_msi_host_init);
static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp)
{
@@ -802,7 +818,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- u32 val, ctrl, num_ctrls;
+ u32 val;
int ret;
/*
@@ -813,20 +829,6 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
dw_pcie_setup(pci);
- if (pp->has_msi_ctrl) {
- num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
-
- /* Initialize IRQ Status array */
- for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
- dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
- (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
- pp->irq_mask[ctrl]);
- dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
- (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
- ~0);
- }
- }
-
dw_pcie_msi_init(pp);
/* Setup RC BARs */
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index fc0872711672..344258aa6b80 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -679,6 +679,9 @@ static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci)
#ifdef CONFIG_PCIE_DW_HOST
irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp);
+void dw_pcie_msi_init(struct dw_pcie_rp *pp);
+int dw_pcie_msi_host_init(struct dw_pcie_rp *pp);
+void dw_pcie_free_msi(struct dw_pcie_rp *pp);
int dw_pcie_setup_rc(struct dw_pcie_rp *pp);
int dw_pcie_host_init(struct dw_pcie_rp *pp);
void dw_pcie_host_deinit(struct dw_pcie_rp *pp);
@@ -691,6 +694,17 @@ static inline irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp)
return IRQ_NONE;
}
+static inline void dw_pcie_msi_init(struct dw_pcie_rp *pp)
+{ }
+
+static inline int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
+{
+ return -ENODEV;
+}
+
+static inline void dw_pcie_free_msi(struct dw_pcie_rp *pp)
+{ }
+
static inline int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
{
return 0;
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v4 2/4] PCI: host-generic: Rename and export gen_pci_init() to allow ECAM creation
2025-05-22 0:14 [PATCH v4 0/4] Add Qualcomm SA8255p based firmware managed PCIe root complex Mayank Rana
2025-05-22 0:14 ` [PATCH v4 1/4] PCI: dwc: Export dwc MSI controller related APIs Mayank Rana
@ 2025-05-22 0:14 ` Mayank Rana
2025-05-22 0:14 ` [PATCH v4 3/4] dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex Mayank Rana
` (2 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Mayank Rana @ 2025-05-22 0:14 UTC (permalink / raw)
To: linux-pci, lpieralisi, kw, robh, bhelgaas, andersson,
manivannan.sadhasivam, krzysztof.kozlowski+dt, conor+dt,
devicetree
Cc: linux-arm-msm, quic_ramkri, quic_nkela, quic_shazhuss,
quic_msarkar, quic_nitegupt, Mayank Rana
Rename gen_pci_init() API as pci_host_common_init() and export it to create
ECAM and initialized ECAM OPs from PCIe driver which don't have way to
populate driver_data as just ECAM ops.
Signed-off-by: Mayank Rana <mayank.rana@oss.qualcomm.com>
---
drivers/pci/controller/pci-host-common.c | 5 +++--
include/linux/pci-ecam.h | 2 ++
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/pci-host-common.c b/drivers/pci/controller/pci-host-common.c
index cf5f59a745b3..6e68c66382fa 100644
--- a/drivers/pci/controller/pci-host-common.c
+++ b/drivers/pci/controller/pci-host-common.c
@@ -20,7 +20,7 @@ static void gen_pci_unmap_cfg(void *ptr)
pci_ecam_free((struct pci_config_window *)ptr);
}
-static struct pci_config_window *gen_pci_init(struct device *dev,
+struct pci_config_window *pci_host_common_init(struct device *dev,
struct pci_host_bridge *bridge, const struct pci_ecam_ops *ops)
{
int err;
@@ -48,6 +48,7 @@ static struct pci_config_window *gen_pci_init(struct device *dev,
return cfg;
}
+EXPORT_SYMBOL_GPL(pci_host_common_init);
int pci_host_common_probe(struct platform_device *pdev)
{
@@ -69,7 +70,7 @@ int pci_host_common_probe(struct platform_device *pdev)
of_pci_check_probe_only();
/* Parse and map our Configuration Space windows */
- cfg = gen_pci_init(dev, bridge, ops);
+ cfg = pci_host_common_init(dev, bridge, ops);
if (IS_ERR(cfg))
return PTR_ERR(cfg);
diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
index 3a4860bd2758..ad6a6170ff26 100644
--- a/include/linux/pci-ecam.h
+++ b/include/linux/pci-ecam.h
@@ -94,5 +94,7 @@ extern const struct pci_ecam_ops loongson_pci_ecam_ops; /* Loongson PCIe */
/* for DT-based PCI controllers that support ECAM */
int pci_host_common_probe(struct platform_device *pdev);
void pci_host_common_remove(struct platform_device *pdev);
+struct pci_config_window *pci_host_common_init(struct device *dev,
+ struct pci_host_bridge *bridge, const struct pci_ecam_ops *ops);
#endif
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v4 3/4] dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex
2025-05-22 0:14 [PATCH v4 0/4] Add Qualcomm SA8255p based firmware managed PCIe root complex Mayank Rana
2025-05-22 0:14 ` [PATCH v4 1/4] PCI: dwc: Export dwc MSI controller related APIs Mayank Rana
2025-05-22 0:14 ` [PATCH v4 2/4] PCI: host-generic: Rename and export gen_pci_init() to allow ECAM creation Mayank Rana
@ 2025-05-22 0:14 ` Mayank Rana
2025-06-04 17:42 ` Mayank Rana
2025-06-05 17:28 ` Rob Herring (Arm)
2025-05-22 0:14 ` [PATCH v4 4/4] PCI: qcom: Add support for Qualcomm SA8255p based " Mayank Rana
2025-06-04 17:38 ` [PATCH v4 0/4] Add Qualcomm SA8255p based firmware managed " Mayank Rana
4 siblings, 2 replies; 11+ messages in thread
From: Mayank Rana @ 2025-05-22 0:14 UTC (permalink / raw)
To: linux-pci, lpieralisi, kw, robh, bhelgaas, andersson,
manivannan.sadhasivam, krzysztof.kozlowski+dt, conor+dt,
devicetree
Cc: linux-arm-msm, quic_ramkri, quic_nkela, quic_shazhuss,
quic_msarkar, quic_nitegupt, Mayank Rana
Document the required configuration to enable the PCIe root complex on
SA8255p, which is managed by firmware using power-domain based handling
and configured as ECAM compliant.
Signed-off-by: Mayank Rana <mayank.rana@oss.qualcomm.com>
---
.../bindings/pci/qcom,pcie-sa8255p.yaml | 122 ++++++++++++++++++
1 file changed, 122 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml
new file mode 100644
index 000000000000..88c8f012708c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-sa8255p.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SA8255p based firmware managed and ECAM compliant PCIe Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description:
+ Qualcomm SA8255p SoC PCIe root complex controller is based on the Synopsys
+ DesignWare PCIe IP which is managed by firmware, and configured in ECAM mode.
+
+properties:
+ compatible:
+ const: qcom,pcie-sa8255p
+
+ reg:
+ description:
+ The Configuration Space base address and size, as accessed from the parent
+ bus. The base address corresponds to the first bus in the "bus-range"
+ property. If no "bus-range" is specified, this will be bus 0 (the
+ default).
+ maxItems: 1
+
+ ranges:
+ description:
+ As described in IEEE Std 1275-1994, but must provide at least a
+ definition of non-prefetchable memory. One or both of prefetchable Memory
+ may also be provided.
+ minItems: 1
+ maxItems: 2
+
+ interrupts:
+ minItems: 8
+ maxItems: 8
+
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+
+ power-domains:
+ maxItems: 1
+
+ dma-coherent: true
+ iommu-map: true
+
+required:
+ - compatible
+ - reg
+ - ranges
+ - power-domains
+ - interrupts
+ - interrupt-names
+
+allOf:
+ - $ref: /schemas/pci/pci-host-bridge.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pci@1c00000 {
+ compatible = "qcom,pcie-sa8255p";
+ reg = <0x4 0x00000000 0 0x10000000>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>,
+ <0x43000000 0x4 0x10100000 0x4 0x10100000 0x0 0x40000000>;
+ bus-range = <0x00 0xff>;
+ dma-coherent;
+ linux,pci-domain = <0>;
+ power-domains = <&scmi5_pd 0>;
+ iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
+ <0x100 &pcie_smmu 0x0001 0x1>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v4 4/4] PCI: qcom: Add support for Qualcomm SA8255p based PCIe root complex
2025-05-22 0:14 [PATCH v4 0/4] Add Qualcomm SA8255p based firmware managed PCIe root complex Mayank Rana
` (2 preceding siblings ...)
2025-05-22 0:14 ` [PATCH v4 3/4] dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex Mayank Rana
@ 2025-05-22 0:14 ` Mayank Rana
2025-06-04 17:38 ` [PATCH v4 0/4] Add Qualcomm SA8255p based firmware managed " Mayank Rana
4 siblings, 0 replies; 11+ messages in thread
From: Mayank Rana @ 2025-05-22 0:14 UTC (permalink / raw)
To: linux-pci, lpieralisi, kw, robh, bhelgaas, andersson,
manivannan.sadhasivam, krzysztof.kozlowski+dt, conor+dt,
devicetree
Cc: linux-arm-msm, quic_ramkri, quic_nkela, quic_shazhuss,
quic_msarkar, quic_nitegupt, Mayank Rana
Add functionality to enable resource management through firmware and
enumerate ECAM compliant root complex on SA8255p ride platform, where
PCIe root complex is firmware managed and configured into ECAM
compliant mode.
Signed-off-by: Mayank Rana <mayank.rana@oss.qualcomm.com>
---
drivers/pci/controller/dwc/Kconfig | 1 +
drivers/pci/controller/dwc/pcie-qcom.c | 114 +++++++++++++++++++++++--
2 files changed, 106 insertions(+), 9 deletions(-)
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index b6d6778b0698..0fe76bd39d69 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -275,6 +275,7 @@ config PCIE_QCOM
select PCIE_DW_HOST
select CRC8
select PCIE_QCOM_COMMON
+ select PCI_HOST_COMMON
help
Say Y here to enable PCIe controller support on Qualcomm SoCs. The
PCIe controller uses the DesignWare core plus Qualcomm-specific
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index dc102d8bd58c..d32b91d5addd 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -21,7 +21,9 @@
#include <linux/limits.h>
#include <linux/init.h>
#include <linux/of.h>
+#include <linux/of_pci.h>
#include <linux/pci.h>
+#include <linux/pci-ecam.h>
#include <linux/pm_opp.h>
#include <linux/pm_runtime.h>
#include <linux/platform_device.h>
@@ -255,10 +257,12 @@ struct qcom_pcie_ops {
* @ops: qcom PCIe ops structure
* @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache
* snooping
+ * @firmware_managed: Set if ecam compliant PCIe root complex is firmware managed
*/
struct qcom_pcie_cfg {
const struct qcom_pcie_ops *ops;
bool override_no_snoop;
+ bool firmware_managed;
bool no_l0s;
};
@@ -1426,6 +1430,10 @@ static const struct qcom_pcie_cfg cfg_sc8280xp = {
.no_l0s = true,
};
+static const struct qcom_pcie_cfg cfg_fw_managed = {
+ .firmware_managed = true,
+};
+
static const struct dw_pcie_ops dw_pcie_ops = {
.link_up = qcom_pcie_link_up,
.start_link = qcom_pcie_start_link,
@@ -1577,6 +1585,50 @@ static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data)
return IRQ_HANDLED;
}
+static void qcom_pci_free_msi(void *ptr)
+{
+ struct dw_pcie_rp *pp = (struct dw_pcie_rp *)ptr;
+
+ if (pp && pp->has_msi_ctrl)
+ dw_pcie_free_msi(pp);
+}
+
+static int qcom_pcie_ecam_host_init(struct pci_config_window *cfg)
+{
+ struct device *dev = cfg->parent;
+ struct dw_pcie_rp *pp;
+ struct dw_pcie *pci;
+ int ret;
+
+ pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
+ if (!pci)
+ return -ENOMEM;
+
+ pci->dev = dev;
+ pp = &pci->pp;
+ pci->dbi_base = cfg->win;
+ pp->num_vectors = MSI_DEF_NUM_VECTORS;
+
+ ret = dw_pcie_msi_host_init(pp);
+ if (ret)
+ return ret;
+
+ pp->has_msi_ctrl = true;
+ dw_pcie_msi_init(pp);
+
+ return devm_add_action_or_reset(dev, qcom_pci_free_msi, pp);
+}
+
+/* ECAM ops */
+static const struct pci_ecam_ops pci_qcom_ecam_ops = {
+ .init = qcom_pcie_ecam_host_init,
+ .pci_ops = {
+ .map_bus = pci_ecam_map_bus,
+ .read = pci_generic_config_read,
+ .write = pci_generic_config_write,
+ }
+};
+
static int qcom_pcie_probe(struct platform_device *pdev)
{
const struct qcom_pcie_cfg *pcie_cfg;
@@ -1591,11 +1643,51 @@ static int qcom_pcie_probe(struct platform_device *pdev)
char *name;
pcie_cfg = of_device_get_match_data(dev);
- if (!pcie_cfg || !pcie_cfg->ops) {
- dev_err(dev, "Invalid platform data\n");
+ if (!pcie_cfg) {
+ dev_err(dev, "No platform data\n");
+ return -EINVAL;
+ }
+
+ if (!pcie_cfg->firmware_managed && !pcie_cfg->ops) {
+ dev_err(dev, "No platform ops\n");
return -EINVAL;
}
+ pm_runtime_enable(dev);
+ ret = pm_runtime_get_sync(dev);
+ if (ret < 0)
+ goto err_pm_runtime_put;
+
+ if (pcie_cfg->firmware_managed) {
+ struct pci_host_bridge *bridge;
+ struct pci_config_window *cfg;
+
+ bridge = devm_pci_alloc_host_bridge(dev, 0);
+ if (!bridge) {
+ ret = -ENOMEM;
+ goto err_pm_runtime_put;
+ }
+
+ /* Parse and map our configuration space windows */
+ cfg = pci_host_common_init(dev, bridge, &pci_qcom_ecam_ops);
+ if (IS_ERR(cfg)) {
+ ret = PTR_ERR(cfg);
+ goto err_pm_runtime_put;
+ }
+
+ bridge->sysdata = cfg;
+ bridge->ops = (struct pci_ops *)&pci_qcom_ecam_ops.pci_ops;
+ bridge->msi_domain = true;
+
+ ret = pci_host_probe(bridge);
+ if (ret) {
+ dev_err(dev, "pci_host_probe() failed:%d\n", ret);
+ goto err_pm_runtime_put;
+ }
+
+ return ret;
+ }
+
pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
if (!pcie)
return -ENOMEM;
@@ -1604,11 +1696,6 @@ static int qcom_pcie_probe(struct platform_device *pdev)
if (!pci)
return -ENOMEM;
- pm_runtime_enable(dev);
- ret = pm_runtime_get_sync(dev);
- if (ret < 0)
- goto err_pm_runtime_put;
-
pci->dev = dev;
pci->ops = &dw_pcie_ops;
pp = &pci->pp;
@@ -1751,9 +1838,13 @@ static int qcom_pcie_probe(struct platform_device *pdev)
static int qcom_pcie_suspend_noirq(struct device *dev)
{
- struct qcom_pcie *pcie = dev_get_drvdata(dev);
+ struct qcom_pcie *pcie;
int ret = 0;
+ pcie = dev_get_drvdata(dev);
+ if (!pcie)
+ return 0;
+
/*
* Set minimum bandwidth required to keep data path functional during
* suspend.
@@ -1807,9 +1898,13 @@ static int qcom_pcie_suspend_noirq(struct device *dev)
static int qcom_pcie_resume_noirq(struct device *dev)
{
- struct qcom_pcie *pcie = dev_get_drvdata(dev);
+ struct qcom_pcie *pcie;
int ret;
+ pcie = dev_get_drvdata(dev);
+ if (!pcie)
+ return 0;
+
if (pm_suspend_target_state != PM_SUSPEND_MEM) {
ret = icc_enable(pcie->icc_cpu);
if (ret) {
@@ -1843,6 +1938,7 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-ipq9574", .data = &cfg_2_9_0 },
{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
+ { .compatible = "qcom,pcie-sa8255p", .data = &cfg_fw_managed },
{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp },
{ .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_34_0},
{ .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v4 0/4] Add Qualcomm SA8255p based firmware managed PCIe root complex
2025-05-22 0:14 [PATCH v4 0/4] Add Qualcomm SA8255p based firmware managed PCIe root complex Mayank Rana
` (3 preceding siblings ...)
2025-05-22 0:14 ` [PATCH v4 4/4] PCI: qcom: Add support for Qualcomm SA8255p based " Mayank Rana
@ 2025-06-04 17:38 ` Mayank Rana
2025-06-12 21:24 ` Mayank Rana
4 siblings, 1 reply; 11+ messages in thread
From: Mayank Rana @ 2025-06-04 17:38 UTC (permalink / raw)
To: linux-pci, lpieralisi, kw, robh, bhelgaas, andersson,
manivannan.sadhasivam, krzysztof.kozlowski+dt, conor+dt,
devicetree
Cc: linux-arm-msm, quic_ramkri, quic_nkela, quic_shazhuss,
quic_msarkar, quic_nitegupt
Hi Mani
As we discussed previously, I resumed working on this functionality.
Please help with reviewing this patchset.
Regards,
Mayank
On 5/21/2025 5:14 PM, Mayank Rana wrote:
> Based on received feedback, this patch series adds support with existing
> Linux qcom-pcie.c driver to get PCIe host root complex functionality on
> Qualcomm SA8255P auto platform.
>
> 1. Interface to allow requesting firmware to manage system resources and
> performing PCIe Link up (devicetree binding in terms of power domain and
> runtime PM APIs is used in driver)
>
> 2. SA8255P is using Synopsys Designware PCIe controller which supports MSI
> controller. Using existing MSI controller based functionality by exporting
> important pcie dwc core driver based MSI APIs, and using those from
> pcie-qcom.c driver.
>
> Below architecture is used on Qualcomm SA8255P auto platform to get ECAM
> compliant PCIe controller based functionality. Here firmware VM based PCIe
> driver takes care of resource management and performing PCIe link related
> handling (D0 and D3cold). Linux pcie-qcom.c driver uses power domain to
> request firmware VM to perform these operations using SCMI interface.
> --------------------
>
>
> ┌────────────────────────┐
> │ │
> ┌──────────────────────┐ │ SHARED MEMORY │ ┌──────────────────────────┐
> │ Firmware VM │ │ │ │ Linux VM │
> │ ┌─────────┐ │ │ │ │ ┌────────────────┐ │
> │ │ Drivers │ ┌──────┐ │ │ │ │ │ PCIE Qcom │ │
> │ │ PCIE PHY◄─┤ │ │ │ ┌────────────────┐ │ │ │ driver │ │
> │ │ │ │ SCMI │ │ │ │ │ │ │ │ │ │
> │ │PCIE CTL │ │ │ ├─────────┼───► PCIE ◄───┼─────┐ │ └──┬──────────▲──┘ │
> │ │ ├─►Server│ │ │ │ SHMEM │ │ │ │ │ │ │
> │ │Clk, Vreg│ │ │ │ │ │ │ │ │ │ ┌──▼──────────┴──┐ │
> │ │GPIO,GDSC│ └─▲──┬─┘ │ │ └────────────────┘ │ └──────┼────┤PCIE SCMI Inst │ │
> │ └─────────┘ │ │ │ │ │ │ └──▲──────────┬──┘ │
> │ │ │ │ │ │ │ │ │ │
> └───────────────┼──┼───┘ │ │ └───────┼──────────┼───────┘
> │ │ │ │ │ │
> │ │ └────────────────────────┘ │ │
> │ │ │ │
> │ │ │ │
> │ │ │ │
> │ │ │IRQ │HVC
> IRQ │ │HVC │ │
> │ │ │ │
> │ │ │ │
> │ │ │ │
> ┌─────────────────┴──▼───────────────────────────────────────────────────────────┴──────────▼──────────────┐
> │ │
> │ │
> │ HYPERVISOR │
> │ │
> │ │
> │ │
> └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
>
> ┌─────────────┐ ┌─────────────┐ ┌──────────┐ ┌───────────┐ ┌─────────────┐ ┌────────────┐
> │ │ │ │ │ │ │ │ │ PCIE │ │ PCIE │
> │ CLOCK │ │ REGULATOR │ │ GPIO │ │ GDSC │ │ PHY │ │ controller │
> └─────────────┘ └─────────────┘ └──────────┘ └───────────┘ └─────────────┘ └────────────┘
> -----------------
> Changes in v4:
> - Addressed provided review comments from reviewers
> Link to v3: https://lore.kernel.org/lkml/20241106221341.2218416-1-quic_mrana@quicinc.com/
>
> Changes in v3:
> - Drop usage of PCIE host generic driver usage, and splitting of MSI functionality
> - Modified existing pcie-qcom.c driver to add support for getting ECAM compliant and firmware managed
> PCIe root complex functionality
> Link to v2: https://lore.kernel.org/linux-arm-kernel/925d1eca-975f-4eec-bdf8-ca07a892361a@quicinc.com/T/
>
> Changes in v2:
> - Drop new PCIe Qcom ECAM driver, and use existing PCIe designware based MSI functionality
> - Add power domain based functionality within existing ECAM driver
> Link to v1: https://lore.kernel.org/all/d10199df-5fb3-407b-b404-a0a4d067341f@quicinc.com/T/
>
> Tested:
> - Validated NVME functionality with PCIe1 on SA8255P-RIDE platform
>
> Mayank Rana (4):
> PCI: dwc: Export dwc MSI controller related APIs
> PCI: host-generic: Rename and export gen_pci_init() API to allow ECAM
> creation
> dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root
> complex
> PCI: qcom: Add Qualcomm SA8255p based PCIe root complex functionality
>
> .../bindings/pci/qcom,pcie-sa8255p.yaml | 103 ++++++++++++++++
> drivers/pci/controller/dwc/Kconfig | 1 +
> .../pci/controller/dwc/pcie-designware-host.c | 38 +++---
> drivers/pci/controller/dwc/pcie-designware.h | 14 +++
> drivers/pci/controller/dwc/pcie-qcom.c | 114 ++++++++++++++++--
> drivers/pci/controller/pci-host-common.c | 5 +-
> include/linux/pci-ecam.h | 2 +
> 7 files changed, 248 insertions(+), 29 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v4 3/4] dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex
2025-05-22 0:14 ` [PATCH v4 3/4] dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex Mayank Rana
@ 2025-06-04 17:42 ` Mayank Rana
2025-06-05 17:28 ` Rob Herring (Arm)
1 sibling, 0 replies; 11+ messages in thread
From: Mayank Rana @ 2025-06-04 17:42 UTC (permalink / raw)
To: linux-pci, lpieralisi, kw, robh, bhelgaas, andersson,
manivannan.sadhasivam, krzysztof.kozlowski+dt, conor+dt,
devicetree
Cc: linux-arm-msm, quic_ramkri, quic_nkela, quic_shazhuss,
quic_msarkar, quic_nitegupt
Hi Krzysztof
Please help with reviewing updated patchset.
Regards,
Mayank
On 5/21/2025 5:14 PM, Mayank Rana wrote:
> Document the required configuration to enable the PCIe root complex on
> SA8255p, which is managed by firmware using power-domain based handling
> and configured as ECAM compliant.
>
> Signed-off-by: Mayank Rana <mayank.rana@oss.qualcomm.com>
> ---
> .../bindings/pci/qcom,pcie-sa8255p.yaml | 122 ++++++++++++++++++
> 1 file changed, 122 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml
> new file mode 100644
> index 000000000000..88c8f012708c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml
> @@ -0,0 +1,122 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/qcom,pcie-sa8255p.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SA8255p based firmware managed and ECAM compliant PCIe Root Complex
> +
> +maintainers:
> + - Bjorn Andersson <andersson@kernel.org>
> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> +
> +description:
> + Qualcomm SA8255p SoC PCIe root complex controller is based on the Synopsys
> + DesignWare PCIe IP which is managed by firmware, and configured in ECAM mode.
> +
> +properties:
> + compatible:
> + const: qcom,pcie-sa8255p
> +
> + reg:
> + description:
> + The Configuration Space base address and size, as accessed from the parent
> + bus. The base address corresponds to the first bus in the "bus-range"
> + property. If no "bus-range" is specified, this will be bus 0 (the
> + default).
> + maxItems: 1
> +
> + ranges:
> + description:
> + As described in IEEE Std 1275-1994, but must provide at least a
> + definition of non-prefetchable memory. One or both of prefetchable Memory
> + may also be provided.
> + minItems: 1
> + maxItems: 2
> +
> + interrupts:
> + minItems: 8
> + maxItems: 8
> +
> + interrupt-names:
> + items:
> + - const: msi0
> + - const: msi1
> + - const: msi2
> + - const: msi3
> + - const: msi4
> + - const: msi5
> + - const: msi6
> + - const: msi7
> +
> + power-domains:
> + maxItems: 1
> +
> + dma-coherent: true
> + iommu-map: true
> +
> +required:
> + - compatible
> + - reg
> + - ranges
> + - power-domains
> + - interrupts
> + - interrupt-names
> +
> +allOf:
> + - $ref: /schemas/pci/pci-host-bridge.yaml#
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + pci@1c00000 {
> + compatible = "qcom,pcie-sa8255p";
> + reg = <0x4 0x00000000 0 0x10000000>;
> + device_type = "pci";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>,
> + <0x43000000 0x4 0x10100000 0x4 0x10100000 0x0 0x40000000>;
> + bus-range = <0x00 0xff>;
> + dma-coherent;
> + linux,pci-domain = <0>;
> + power-domains = <&scmi5_pd 0>;
> + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
> + <0x100 &pcie_smmu 0x0001 0x1>;
> + interrupt-parent = <&intc>;
> + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi0", "msi1", "msi2", "msi3",
> + "msi4", "msi5", "msi6", "msi7";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
> +
> + pcie@0 {
> + device_type = "pci";
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + bus-range = <0x01 0xff>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges;
> + };
> + };
> + };
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v4 3/4] dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex
2025-05-22 0:14 ` [PATCH v4 3/4] dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex Mayank Rana
2025-06-04 17:42 ` Mayank Rana
@ 2025-06-05 17:28 ` Rob Herring (Arm)
1 sibling, 0 replies; 11+ messages in thread
From: Rob Herring (Arm) @ 2025-06-05 17:28 UTC (permalink / raw)
To: Mayank Rana
Cc: manivannan.sadhasivam, linux-arm-msm, quic_nkela, linux-pci,
quic_msarkar, quic_shazhuss, krzysztof.kozlowski+dt, lpieralisi,
kw, conor+dt, quic_ramkri, bhelgaas, devicetree, quic_nitegupt,
andersson
On Wed, 21 May 2025 17:14:24 -0700, Mayank Rana wrote:
> Document the required configuration to enable the PCIe root complex on
> SA8255p, which is managed by firmware using power-domain based handling
> and configured as ECAM compliant.
>
> Signed-off-by: Mayank Rana <mayank.rana@oss.qualcomm.com>
> ---
> .../bindings/pci/qcom,pcie-sa8255p.yaml | 122 ++++++++++++++++++
> 1 file changed, 122 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v4 0/4] Add Qualcomm SA8255p based firmware managed PCIe root complex
2025-06-04 17:38 ` [PATCH v4 0/4] Add Qualcomm SA8255p based firmware managed " Mayank Rana
@ 2025-06-12 21:24 ` Mayank Rana
2025-06-13 9:29 ` Manivannan Sadhasivam
0 siblings, 1 reply; 11+ messages in thread
From: Mayank Rana @ 2025-06-12 21:24 UTC (permalink / raw)
To: linux-pci, lpieralisi, kw, robh, bhelgaas, andersson,
manivannan.sadhasivam, krzysztof.kozlowski+dt, conor+dt,
devicetree, Manivannan Sadhasivam
Cc: linux-arm-msm, quic_ramkri, quic_shazhuss, quic_msarkar,
quic_nitegupt
Hi Mani
Gentle reminder for review.
Regards
Mayank
On 6/4/2025 10:38 AM, Mayank Rana wrote:
> Hi Mani
>
> As we discussed previously, I resumed working on this functionality.
> Please help with reviewing this patchset.
>
> Regards,
> Mayank
> On 5/21/2025 5:14 PM, Mayank Rana wrote:
>> Based on received feedback, this patch series adds support with existing
>> Linux qcom-pcie.c driver to get PCIe host root complex functionality on
>> Qualcomm SA8255P auto platform.
>>
>> 1. Interface to allow requesting firmware to manage system resources and
>> performing PCIe Link up (devicetree binding in terms of power domain and
>> runtime PM APIs is used in driver)
>>
>> 2. SA8255P is using Synopsys Designware PCIe controller which supports
>> MSI
>> controller. Using existing MSI controller based functionality by
>> exporting
>> important pcie dwc core driver based MSI APIs, and using those from
>> pcie-qcom.c driver.
>>
>> Below architecture is used on Qualcomm SA8255P auto platform to get ECAM
>> compliant PCIe controller based functionality. Here firmware VM based
>> PCIe
>> driver takes care of resource management and performing PCIe link related
>> handling (D0 and D3cold). Linux pcie-qcom.c driver uses power domain to
>> request firmware VM to perform these operations using SCMI interface.
>> --------------------
>>
>>
>> ┌────────────────────────┐
>> │ │
>> ┌──────────────────────┐ │ SHARED MEMORY
>> │ ┌──────────────────────────┐
>> │ Firmware VM │ │
>> │ │ Linux VM │
>> │ ┌─────────┐ │ │
>> │ │ ┌────────────────┐ │
>> │ │ Drivers │ ┌──────┐ │ │
>> │ │ │ PCIE Qcom │ │
>> │ │ PCIE PHY◄─┤ │ │ │ ┌────────────────┐
>> │ │ │ driver │ │
>> │ │ │ │ SCMI │ │ │ │ │
>> │ │ │ │ │
>> │ │PCIE CTL │ │ │ ├─────────┼───► PCIE
>> ◄───┼─────┐ │ └──┬──────────▲──┘ │
>> │ │ ├─►Server│ │ │ │ SHMEM │ │
>> │ │ │ │ │
>> │ │Clk, Vreg│ │ │ │ │ │ │ │
>> │ │ ┌──▼──────────┴──┐ │
>> │ │GPIO,GDSC│ └─▲──┬─┘ │ │ └────────────────┘ │
>> └──────┼────┤PCIE SCMI Inst │ │
>> │ └─────────┘ │ │ │ │
>> │ │ └──▲──────────┬──┘ │
>> │ │ │ │ │
>> │ │ │ │ │
>> └───────────────┼──┼───┘ │
>> │ └───────┼──────────┼───────┘
>> │ │ │
>> │ │ │
>> │ │
>> └────────────────────────┘ │ │
>> │
>> │ │ │
>> │
>> │ │ │
>> │
>> │ │ │
>> │
>> │ │IRQ
>> │HVC
>> IRQ │
>> │HVC │ │
>> │
>> │ │ │
>> │
>> │ │ │
>> │
>> │ │ │
>> ┌─────────────────┴──▼───────────────────────────────────────────────────────────┴──────────▼──────────────┐
>> │ │
>> │ │
>> │
>> HYPERVISOR │
>> │ │
>> │ │
>> │ │
>> └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
>> ┌─────────────┐ ┌─────────────┐ ┌──────────┐ ┌───────────┐
>> ┌─────────────┐ ┌────────────┐
>> │ │ │ │ │ │ │ │
>> │ PCIE │ │ PCIE │
>> │ CLOCK │ │ REGULATOR │ │ GPIO │ │ GDSC │
>> │ PHY │ │ controller │
>> └─────────────┘ └─────────────┘ └──────────┘ └───────────┘
>> └─────────────┘ └────────────┘
>> -----------------
>> Changes in v4:
>> - Addressed provided review comments from reviewers
>> Link to v3: https://lore.kernel.org/lkml/20241106221341.2218416-1-
>> quic_mrana@quicinc.com/
>>
>> Changes in v3:
>> - Drop usage of PCIE host generic driver usage, and splitting of MSI
>> functionality
>> - Modified existing pcie-qcom.c driver to add support for getting ECAM
>> compliant and firmware managed
>> PCIe root complex functionality
>> Link to v2: https://lore.kernel.org/linux-arm-
>> kernel/925d1eca-975f-4eec-bdf8-ca07a892361a@quicinc.com/T/
>>
>> Changes in v2:
>> - Drop new PCIe Qcom ECAM driver, and use existing PCIe designware
>> based MSI functionality
>> - Add power domain based functionality within existing ECAM driver
>> Link to v1: https://lore.kernel.org/all/d10199df-5fb3-407b-b404-
>> a0a4d067341f@quicinc.com/T/
>>
>> Tested:
>> - Validated NVME functionality with PCIe1 on SA8255P-RIDE platform
>>
>> Mayank Rana (4):
>> PCI: dwc: Export dwc MSI controller related APIs
>> PCI: host-generic: Rename and export gen_pci_init() API to allow ECAM
>> creation
>> dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root
>> complex
>> PCI: qcom: Add Qualcomm SA8255p based PCIe root complex functionality
>>
>> .../bindings/pci/qcom,pcie-sa8255p.yaml | 103 ++++++++++++++++
>> drivers/pci/controller/dwc/Kconfig | 1 +
>> .../pci/controller/dwc/pcie-designware-host.c | 38 +++---
>> drivers/pci/controller/dwc/pcie-designware.h | 14 +++
>> drivers/pci/controller/dwc/pcie-qcom.c | 114 ++++++++++++++++--
>> drivers/pci/controller/pci-host-common.c | 5 +-
>> include/linux/pci-ecam.h | 2 +
>> 7 files changed, 248 insertions(+), 29 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-
>> sa8255p.yaml
>>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v4 0/4] Add Qualcomm SA8255p based firmware managed PCIe root complex
2025-06-12 21:24 ` Mayank Rana
@ 2025-06-13 9:29 ` Manivannan Sadhasivam
2025-06-16 18:08 ` Mayank Rana
0 siblings, 1 reply; 11+ messages in thread
From: Manivannan Sadhasivam @ 2025-06-13 9:29 UTC (permalink / raw)
To: Mayank Rana
Cc: linux-pci, lpieralisi, kw, robh, bhelgaas, andersson,
manivannan.sadhasivam, krzysztof.kozlowski+dt, conor+dt,
devicetree, linux-arm-msm, quic_ramkri, quic_shazhuss,
quic_msarkar, quic_nitegupt
On Thu, Jun 12, 2025 at 02:24:04PM -0700, Mayank Rana wrote:
> Hi Mani
>
> Gentle reminder for review.
>
These patches are not applying on top of v6.16-rc1. Please post the rebased
version.
- Mani
> Regards
> Mayank
>
> On 6/4/2025 10:38 AM, Mayank Rana wrote:
> > Hi Mani
> >
> > As we discussed previously, I resumed working on this functionality.
> > Please help with reviewing this patchset.
> >
> > Regards,
> > Mayank
> > On 5/21/2025 5:14 PM, Mayank Rana wrote:
> > > Based on received feedback, this patch series adds support with existing
> > > Linux qcom-pcie.c driver to get PCIe host root complex functionality on
> > > Qualcomm SA8255P auto platform.
> > >
> > > 1. Interface to allow requesting firmware to manage system resources and
> > > performing PCIe Link up (devicetree binding in terms of power domain and
> > > runtime PM APIs is used in driver)
> > >
> > > 2. SA8255P is using Synopsys Designware PCIe controller which
> > > supports MSI
> > > controller. Using existing MSI controller based functionality by
> > > exporting
> > > important pcie dwc core driver based MSI APIs, and using those from
> > > pcie-qcom.c driver.
> > >
> > > Below architecture is used on Qualcomm SA8255P auto platform to get ECAM
> > > compliant PCIe controller based functionality. Here firmware VM
> > > based PCIe
> > > driver takes care of resource management and performing PCIe link related
> > > handling (D0 and D3cold). Linux pcie-qcom.c driver uses power domain to
> > > request firmware VM to perform these operations using SCMI interface.
> > > --------------------
> > >
> > >
> > > ┌────────────────────────┐
> > > │ │
> > > ┌──────────────────────┐ │ SHARED MEMORY
> > > │ ┌──────────────────────────┐
> > > │ Firmware VM │ │
> > > │ │ Linux VM │
> > > │ ┌─────────┐ │ │
> > > │ │ ┌────────────────┐ │
> > > │ │ Drivers │ ┌──────┐ │ │
> > > │ │ │ PCIE Qcom │ │
> > > │ │ PCIE PHY◄─┤ │ │ │ ┌────────────────┐
> > > │ │ │ driver │ │
> > > │ │ │ │ SCMI │ │ │ │ │
> > > │ │ │ │ │
> > > │ │PCIE CTL │ │ │ ├─────────┼───► PCIE
> > > ◄───┼─────┐ │ └──┬──────────▲──┘ │
> > > │ │ ├─►Server│ │ │ │ SHMEM │ │
> > > │ │ │ │ │
> > > │ │Clk, Vreg│ │ │ │ │ │ │ │
> > > │ │ ┌──▼──────────┴──┐ │
> > > │ │GPIO,GDSC│ └─▲──┬─┘ │ │ └────────────────┘ │
> > > └──────┼────┤PCIE SCMI Inst │ │
> > > │ └─────────┘ │ │ │ │
> > > │ │ └──▲──────────┬──┘ │
> > > │ │ │ │ │
> > > │ │ │ │ │
> > > └───────────────┼──┼───┘ │
> > > │ └───────┼──────────┼───────┘
> > > │ │ │
> > > │ │ │
> > > │ │
> > > └────────────────────────┘ │ │
> > > │
> > > │
> > > │ │
> > > │
> > > │
> > > │ │
> > > │
> > > │
> > > │ │
> > > │
> > > │ │IRQ
> > > │HVC
> > > IRQ │
> > > │HVC
> > > │ │
> > > │
> > > │
> > > │ │
> > > │
> > > │
> > > │ │
> > > │
> > > │
> > > │ │
> > > ┌─────────────────┴──▼───────────────────────────────────────────────────────────┴──────────▼──────────────┐
> > > │ │
> > > │ │
> > > │
> > > HYPERVISOR
> > > │
> > > │ │
> > > │ │
> > > │ │
> > > └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
> > > ┌─────────────┐ ┌─────────────┐ ┌──────────┐ ┌───────────┐
> > > ┌─────────────┐ ┌────────────┐
> > > │ │ │ │ │ │ │ │
> > > │ PCIE │ │ PCIE │
> > > │ CLOCK │ │ REGULATOR │ │ GPIO │ │ GDSC │
> > > │ PHY │ │ controller │
> > > └─────────────┘ └─────────────┘ └──────────┘ └───────────┘
> > > └─────────────┘ └────────────┘
> > > -----------------
> > > Changes in v4:
> > > - Addressed provided review comments from reviewers
> > > Link to v3: https://lore.kernel.org/lkml/20241106221341.2218416-1-
> > > quic_mrana@quicinc.com/
> > >
> > > Changes in v3:
> > > - Drop usage of PCIE host generic driver usage, and splitting of MSI
> > > functionality
> > > - Modified existing pcie-qcom.c driver to add support for getting
> > > ECAM compliant and firmware managed
> > > PCIe root complex functionality
> > > Link to v2: https://lore.kernel.org/linux-arm-
> > > kernel/925d1eca-975f-4eec-bdf8-ca07a892361a@quicinc.com/T/
> > >
> > > Changes in v2:
> > > - Drop new PCIe Qcom ECAM driver, and use existing PCIe designware
> > > based MSI functionality
> > > - Add power domain based functionality within existing ECAM driver
> > > Link to v1: https://lore.kernel.org/all/d10199df-5fb3-407b-b404-
> > > a0a4d067341f@quicinc.com/T/
> > >
> > > Tested:
> > > - Validated NVME functionality with PCIe1 on SA8255P-RIDE platform
> > >
> > > Mayank Rana (4):
> > > PCI: dwc: Export dwc MSI controller related APIs
> > > PCI: host-generic: Rename and export gen_pci_init() API to allow ECAM
> > > creation
> > > dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root
> > > complex
> > > PCI: qcom: Add Qualcomm SA8255p based PCIe root complex functionality
> > >
> > > .../bindings/pci/qcom,pcie-sa8255p.yaml | 103 ++++++++++++++++
> > > drivers/pci/controller/dwc/Kconfig | 1 +
> > > .../pci/controller/dwc/pcie-designware-host.c | 38 +++---
> > > drivers/pci/controller/dwc/pcie-designware.h | 14 +++
> > > drivers/pci/controller/dwc/pcie-qcom.c | 114 ++++++++++++++++--
> > > drivers/pci/controller/pci-host-common.c | 5 +-
> > > include/linux/pci-ecam.h | 2 +
> > > 7 files changed, 248 insertions(+), 29 deletions(-)
> > > create mode 100644
> > > Documentation/devicetree/bindings/pci/qcom,pcie- sa8255p.yaml
> > >
> >
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v4 0/4] Add Qualcomm SA8255p based firmware managed PCIe root complex
2025-06-13 9:29 ` Manivannan Sadhasivam
@ 2025-06-16 18:08 ` Mayank Rana
0 siblings, 0 replies; 11+ messages in thread
From: Mayank Rana @ 2025-06-16 18:08 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: linux-pci, lpieralisi, kw, robh, bhelgaas, andersson,
manivannan.sadhasivam, krzysztof.kozlowski+dt, conor+dt,
devicetree, linux-arm-msm, quic_ramkri, quic_shazhuss,
quic_msarkar, quic_nitegupt
Hi Mani
On 6/13/2025 2:29 AM, Manivannan Sadhasivam wrote:
> On Thu, Jun 12, 2025 at 02:24:04PM -0700, Mayank Rana wrote:
>> Hi Mani
>>
>> Gentle reminder for review.
>>
>
> These patches are not applying on top of v6.16-rc1. Please post the rebased
> version.
ok. will rebase changes and resend it.
Thanks.
Regards,
Mayank
> - Mani
>
>> Regards
>> Mayank
>>
>> On 6/4/2025 10:38 AM, Mayank Rana wrote:
>>> Hi Mani
>>>
>>> As we discussed previously, I resumed working on this functionality.
>>> Please help with reviewing this patchset.
>>>
>>> Regards,
>>> Mayank
>>> On 5/21/2025 5:14 PM, Mayank Rana wrote:
>>>> Based on received feedback, this patch series adds support with existing
>>>> Linux qcom-pcie.c driver to get PCIe host root complex functionality on
>>>> Qualcomm SA8255P auto platform.
>>>>
>>>> 1. Interface to allow requesting firmware to manage system resources and
>>>> performing PCIe Link up (devicetree binding in terms of power domain and
>>>> runtime PM APIs is used in driver)
>>>>
>>>> 2. SA8255P is using Synopsys Designware PCIe controller which
>>>> supports MSI
>>>> controller. Using existing MSI controller based functionality by
>>>> exporting
>>>> important pcie dwc core driver based MSI APIs, and using those from
>>>> pcie-qcom.c driver.
>>>>
>>>> Below architecture is used on Qualcomm SA8255P auto platform to get ECAM
>>>> compliant PCIe controller based functionality. Here firmware VM
>>>> based PCIe
>>>> driver takes care of resource management and performing PCIe link related
>>>> handling (D0 and D3cold). Linux pcie-qcom.c driver uses power domain to
>>>> request firmware VM to perform these operations using SCMI interface.
>>>> --------------------
>>>>
>>>>
>>>> ┌────────────────────────┐
>>>> │ │
>>>> ┌──────────────────────┐ │ SHARED MEMORY
>>>> │ ┌──────────────────────────┐
>>>> │ Firmware VM │ │
>>>> │ │ Linux VM │
>>>> │ ┌─────────┐ │ │
>>>> │ │ ┌────────────────┐ │
>>>> │ │ Drivers │ ┌──────┐ │ │
>>>> │ │ │ PCIE Qcom │ │
>>>> │ │ PCIE PHY◄─┤ │ │ │ ┌────────────────┐
>>>> │ │ │ driver │ │
>>>> │ │ │ │ SCMI │ │ │ │ │
>>>> │ │ │ │ │
>>>> │ │PCIE CTL │ │ │ ├─────────┼───► PCIE
>>>> ◄───┼─────┐ │ └──┬──────────▲──┘ │
>>>> │ │ ├─►Server│ │ │ │ SHMEM │ │
>>>> │ │ │ │ │
>>>> │ │Clk, Vreg│ │ │ │ │ │ │ │
>>>> │ │ ┌──▼──────────┴──┐ │
>>>> │ │GPIO,GDSC│ └─▲──┬─┘ │ │ └────────────────┘ │
>>>> └──────┼────┤PCIE SCMI Inst │ │
>>>> │ └─────────┘ │ │ │ │
>>>> │ │ └──▲──────────┬──┘ │
>>>> │ │ │ │ │
>>>> │ │ │ │ │
>>>> └───────────────┼──┼───┘ │
>>>> │ └───────┼──────────┼───────┘
>>>> │ │ │
>>>> │ │ │
>>>> │ │
>>>> └────────────────────────┘ │ │
>>>> │
>>>> │
>>>> │ │
>>>> │
>>>> │
>>>> │ │
>>>> │
>>>> │
>>>> │ │
>>>> │
>>>> │ │IRQ
>>>> │HVC
>>>> IRQ │
>>>> │HVC
>>>> │ │
>>>> │
>>>> │
>>>> │ │
>>>> │
>>>> │
>>>> │ │
>>>> │
>>>> │
>>>> │ │
>>>> ┌─────────────────┴──▼───────────────────────────────────────────────────────────┴──────────▼──────────────┐
>>>> │ │
>>>> │ │
>>>> │
>>>> HYPERVISOR
>>>> │
>>>> │ │
>>>> │ │
>>>> │ │
>>>> └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
>>>> ┌─────────────┐ ┌─────────────┐ ┌──────────┐ ┌───────────┐
>>>> ┌─────────────┐ ┌────────────┐
>>>> │ │ │ │ │ │ │ │
>>>> │ PCIE │ │ PCIE │
>>>> │ CLOCK │ │ REGULATOR │ │ GPIO │ │ GDSC │
>>>> │ PHY │ │ controller │
>>>> └─────────────┘ └─────────────┘ └──────────┘ └───────────┘
>>>> └─────────────┘ └────────────┘
>>>> -----------------
>>>> Changes in v4:
>>>> - Addressed provided review comments from reviewers
>>>> Link to v3: https://lore.kernel.org/lkml/20241106221341.2218416-1-
>>>> quic_mrana@quicinc.com/
>>>>
>>>> Changes in v3:
>>>> - Drop usage of PCIE host generic driver usage, and splitting of MSI
>>>> functionality
>>>> - Modified existing pcie-qcom.c driver to add support for getting
>>>> ECAM compliant and firmware managed
>>>> PCIe root complex functionality
>>>> Link to v2: https://lore.kernel.org/linux-arm-
>>>> kernel/925d1eca-975f-4eec-bdf8-ca07a892361a@quicinc.com/T/
>>>>
>>>> Changes in v2:
>>>> - Drop new PCIe Qcom ECAM driver, and use existing PCIe designware
>>>> based MSI functionality
>>>> - Add power domain based functionality within existing ECAM driver
>>>> Link to v1: https://lore.kernel.org/all/d10199df-5fb3-407b-b404-
>>>> a0a4d067341f@quicinc.com/T/
>>>>
>>>> Tested:
>>>> - Validated NVME functionality with PCIe1 on SA8255P-RIDE platform
>>>>
>>>> Mayank Rana (4):
>>>> PCI: dwc: Export dwc MSI controller related APIs
>>>> PCI: host-generic: Rename and export gen_pci_init() API to allow ECAM
>>>> creation
>>>> dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root
>>>> complex
>>>> PCI: qcom: Add Qualcomm SA8255p based PCIe root complex functionality
>>>>
>>>> .../bindings/pci/qcom,pcie-sa8255p.yaml | 103 ++++++++++++++++
>>>> drivers/pci/controller/dwc/Kconfig | 1 +
>>>> .../pci/controller/dwc/pcie-designware-host.c | 38 +++---
>>>> drivers/pci/controller/dwc/pcie-designware.h | 14 +++
>>>> drivers/pci/controller/dwc/pcie-qcom.c | 114 ++++++++++++++++--
>>>> drivers/pci/controller/pci-host-common.c | 5 +-
>>>> include/linux/pci-ecam.h | 2 +
>>>> 7 files changed, 248 insertions(+), 29 deletions(-)
>>>> create mode 100644
>>>> Documentation/devicetree/bindings/pci/qcom,pcie- sa8255p.yaml
>>>>
>>>
>>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2025-06-16 18:08 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-05-22 0:14 [PATCH v4 0/4] Add Qualcomm SA8255p based firmware managed PCIe root complex Mayank Rana
2025-05-22 0:14 ` [PATCH v4 1/4] PCI: dwc: Export dwc MSI controller related APIs Mayank Rana
2025-05-22 0:14 ` [PATCH v4 2/4] PCI: host-generic: Rename and export gen_pci_init() to allow ECAM creation Mayank Rana
2025-05-22 0:14 ` [PATCH v4 3/4] dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex Mayank Rana
2025-06-04 17:42 ` Mayank Rana
2025-06-05 17:28 ` Rob Herring (Arm)
2025-05-22 0:14 ` [PATCH v4 4/4] PCI: qcom: Add support for Qualcomm SA8255p based " Mayank Rana
2025-06-04 17:38 ` [PATCH v4 0/4] Add Qualcomm SA8255p based firmware managed " Mayank Rana
2025-06-12 21:24 ` Mayank Rana
2025-06-13 9:29 ` Manivannan Sadhasivam
2025-06-16 18:08 ` Mayank Rana
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