From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75B5FC43334 for ; Wed, 13 Jul 2022 08:20:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235498AbiGMIUk (ORCPT ); Wed, 13 Jul 2022 04:20:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234715AbiGMIUW (ORCPT ); Wed, 13 Jul 2022 04:20:22 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 534B9ECBBB for ; Wed, 13 Jul 2022 01:16:24 -0700 (PDT) Received: from gallifrey.ext.pengutronix.de ([2001:67c:670:201:5054:ff:fe8d:eefb] helo=[IPv6:::1]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1oBXXd-00089u-7b; Wed, 13 Jul 2022 10:16:17 +0200 Message-ID: <724610978fc8c1a5dbf23fa36e3f57c8df3fb326.camel@pengutronix.de> Subject: Re: [PATCH v14 03/17] PCI: imx6: Move imx6_pcie_enable_ref_clk() earlier From: Lucas Stach To: Richard Zhu , bhelgaas@google.com, robh+dt@kernel.org, broonie@kernel.org, lorenzo.pieralisi@arm.com, festevam@gmail.com, francesco.dolcini@toradex.com Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Date: Wed, 13 Jul 2022 10:16:16 +0200 In-Reply-To: <1656645935-1370-4-git-send-email-hongxing.zhu@nxp.com> References: <1656645935-1370-1-git-send-email-hongxing.zhu@nxp.com> <1656645935-1370-4-git-send-email-hongxing.zhu@nxp.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.40.4 (3.40.4-1.fc34) MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2001:67c:670:201:5054:ff:fe8d:eefb X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-pci@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Am Freitag, dem 01.07.2022 um 11:25 +0800 schrieb Richard Zhu: > From: Bjorn Helgaas > > Move imx6_pcie_enable_ref_clk() earlier so it's not in the middle between > imx6_pcie_assert_core_reset() and imx6_pcie_deassert_core_reset(). No > functional change intended. > > Signed-off-by: Bjorn Helgaas > Acked-by: Richard Zhu Reviewed-by: Lucas Stach > --- > drivers/pci/controller/dwc/pci-imx6.c | 96 +++++++++++++-------------- > 1 file changed, 48 insertions(+), 48 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index e63eb6380020..a6d2b907d42b 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -520,54 +520,6 @@ static int imx6_pcie_attach_pd(struct device *dev) > return 0; > } > > -static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) > -{ > - struct device *dev = imx6_pcie->pci->dev; > - > - switch (imx6_pcie->drvdata->variant) { > - case IMX7D: > - case IMX8MQ: > - reset_control_assert(imx6_pcie->pciephy_reset); > - fallthrough; > - case IMX8MM: > - reset_control_assert(imx6_pcie->apps_reset); > - break; > - case IMX6SX: > - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, > - IMX6SX_GPR12_PCIE_TEST_POWERDOWN, > - IMX6SX_GPR12_PCIE_TEST_POWERDOWN); > - /* Force PCIe PHY reset */ > - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, > - IMX6SX_GPR5_PCIE_BTNRST_RESET, > - IMX6SX_GPR5_PCIE_BTNRST_RESET); > - break; > - case IMX6QP: > - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_SW_RST, > - IMX6Q_GPR1_PCIE_SW_RST); > - break; > - case IMX6Q: > - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); > - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); > - break; > - } > - > - if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) { > - int ret = regulator_disable(imx6_pcie->vpcie); > - > - if (ret) > - dev_err(dev, "failed to disable vpcie regulator: %d\n", > - ret); > - } > - > - /* Some boards don't have PCIe reset GPIO. */ > - if (gpio_is_valid(imx6_pcie->reset_gpio)) > - gpio_set_value_cansleep(imx6_pcie->reset_gpio, > - imx6_pcie->gpio_active_high); > -} > - > static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) > { > struct dw_pcie *pci = imx6_pcie->pci; > @@ -628,6 +580,54 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) > return ret; > } > > +static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) > +{ > + struct device *dev = imx6_pcie->pci->dev; > + > + switch (imx6_pcie->drvdata->variant) { > + case IMX7D: > + case IMX8MQ: > + reset_control_assert(imx6_pcie->pciephy_reset); > + fallthrough; > + case IMX8MM: > + reset_control_assert(imx6_pcie->apps_reset); > + break; > + case IMX6SX: > + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, > + IMX6SX_GPR12_PCIE_TEST_POWERDOWN, > + IMX6SX_GPR12_PCIE_TEST_POWERDOWN); > + /* Force PCIe PHY reset */ > + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, > + IMX6SX_GPR5_PCIE_BTNRST_RESET, > + IMX6SX_GPR5_PCIE_BTNRST_RESET); > + break; > + case IMX6QP: > + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, > + IMX6Q_GPR1_PCIE_SW_RST, > + IMX6Q_GPR1_PCIE_SW_RST); > + break; > + case IMX6Q: > + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, > + IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, > + IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); > + break; > + } > + > + if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) { > + int ret = regulator_disable(imx6_pcie->vpcie); > + > + if (ret) > + dev_err(dev, "failed to disable vpcie regulator: %d\n", > + ret); > + } > + > + /* Some boards don't have PCIe reset GPIO. */ > + if (gpio_is_valid(imx6_pcie->reset_gpio)) > + gpio_set_value_cansleep(imx6_pcie->reset_gpio, > + imx6_pcie->gpio_active_high); > +} > + > static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) > { > struct dw_pcie *pci = imx6_pcie->pci; > -- > 2.25.1 >