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Box" , Kai-Heng Feng , "Rafael J. Wysocki" , Heiner Kallweit , Chia-Lin Kao , Bjorn Helgaas , "linux-tegra@vger.kernel.org" References: <20250922-pci-dt-aspm-v2-0-2a65cf84e326@oss.qualcomm.com> <20250922-pci-dt-aspm-v2-1-2a65cf84e326@oss.qualcomm.com> From: Jon Hunter Content-Language: en-US In-Reply-To: <20250922-pci-dt-aspm-v2-1-2a65cf84e326@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: LO4P265CA0322.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:390::16) To DS2PR12MB9750.namprd12.prod.outlook.com (2603:10b6:8:2b0::12) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PR12MB9750:EE_|IA1PR12MB6114:EE_ X-MS-Office365-Filtering-Correlation-Id: f8f45e30-1085-40e0-722d-08de59af8e89 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|1800799024|7053199007; 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So the PCI subsystem ended up trusting the BIOS to enable only the > ASPM states that were known to work for the devices. > > But this turned out to be a problem for devicetree platforms, especially > the ARM based devicetree platforms powering Embedded and *some* Compute > devices as they tend to run without any standard BIOS. So the ASPM states > on these platforms were left disabled during boot and the PCI subsystem > never bothered to enable them, unless the user has forcefully enabled the > ASPM states through Kconfig, cmdline, and sysfs or the device drivers > themselves, enabling the ASPM states through pci_enable_link_state() APIs. > > This caused runtime power issues on those platforms. So a couple of > approaches were tried to mitigate this BIOS dependency without user > intervention by enabling the ASPM states in the PCI controller drivers > after device enumeration, and overriding the ASPM/Clock PM states > by the PCI controller drivers through an API before enumeration. > > But it has been concluded that none of these mitigations should really be > required and the PCI subsystem should enable the ASPM states advertised by > the devices without relying on BIOS or the PCI controller drivers. If any > device is found to be misbehaving after enabling ASPM states that they > advertised, then those devices should be quirked to disable the problematic > ASPM/Clock PM states. > > In an effort to do so, start by overriding the ASPM and Clock PM states set > by the BIOS for devicetree platforms first. Separate helper functions are > introduced to override the BIOS set states by enabling all of them if > of_have_populated_dt() returns true. To aid debugging, print the overridden > ASPM and Clock PM states as well. > > In the future, these helpers could be extended to allow other platforms > like VMD, newer ACPI systems with a cutoff year etc... to follow the path. > > Link: https://lore.kernel.org/linux-pci/20250828204345.GA958461@bhelgaas > Suggested-by: Bjorn Helgaas > Signed-off-by: Manivannan Sadhasivam > Link: https://patch.msgid.link/20250916-pci-dt-aspm-v1-1-778fe907c9ad@oss.qualcomm.com > --- > drivers/pci/pcie/aspm.c | 42 ++++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 40 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c > index 919a05b9764791c3cc469c9ada62ba5b2c405118..cda31150aec1b67b6a48b60569222ea3d1c3d41f 100644 > --- a/drivers/pci/pcie/aspm.c > +++ b/drivers/pci/pcie/aspm.c > @@ -15,6 +15,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -235,13 +236,15 @@ struct pcie_link_state { > u32 aspm_support:7; /* Supported ASPM state */ > u32 aspm_enabled:7; /* Enabled ASPM state */ > u32 aspm_capable:7; /* Capable ASPM state with latency */ > - u32 aspm_default:7; /* Default ASPM state by BIOS */ > + u32 aspm_default:7; /* Default ASPM state by BIOS or > + override */ > u32 aspm_disable:7; /* Disabled ASPM state */ > > /* Clock PM state */ > u32 clkpm_capable:1; /* Clock PM capable? */ > u32 clkpm_enabled:1; /* Current Clock PM state */ > - u32 clkpm_default:1; /* Default Clock PM state by BIOS */ > + u32 clkpm_default:1; /* Default Clock PM state by BIOS or > + override */ > u32 clkpm_disable:1; /* Clock PM disabled */ > }; > > @@ -373,6 +376,18 @@ static void pcie_set_clkpm(struct pcie_link_state *link, int enable) > pcie_set_clkpm_nocheck(link, enable); > } > > +static void pcie_clkpm_override_default_link_state(struct pcie_link_state *link, > + int enabled) > +{ > + struct pci_dev *pdev = link->downstream; > + > + /* Override the BIOS disabled Clock PM state for devicetree platforms */ > + if (of_have_populated_dt() && !enabled) { > + link->clkpm_default = 1; > + pci_info(pdev, "Clock PM state overridden: ClockPM+\n"); > + } > +} > + > static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) > { > int capable = 1, enabled = 1; > @@ -395,6 +410,7 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) > } > link->clkpm_enabled = enabled; > link->clkpm_default = enabled; > + pcie_clkpm_override_default_link_state(link, enabled); > link->clkpm_capable = capable; > link->clkpm_disable = blacklist ? 1 : 0; > } > @@ -788,6 +804,26 @@ static void aspm_l1ss_init(struct pcie_link_state *link) > aspm_calc_l12_info(link, parent_l1ss_cap, child_l1ss_cap); > } > > +static void pcie_aspm_override_default_link_state(struct pcie_link_state *link) > +{ > + struct pci_dev *pdev = link->downstream; > + u32 override; > + > + /* Override the BIOS disabled ASPM states for devicetree platforms */ > + if (of_have_populated_dt()) { > + link->aspm_default = PCIE_LINK_STATE_ASPM_ALL; > + override = link->aspm_default & ~link->aspm_enabled; > + if (override) > + pci_info(pdev, "ASPM states overridden: %s%s%s%s%s%s\n", > + (override & PCIE_LINK_STATE_L0S) ? "L0s+, " : "", > + (override & PCIE_LINK_STATE_L1) ? "L1+, " : "", > + (override & PCIE_LINK_STATE_L1_1) ? "L1.1+, " : "", > + (override & PCIE_LINK_STATE_L1_2) ? "L1.2+, " : "", > + (override & PCIE_LINK_STATE_L1_1_PCIPM) ? "L1.1 PCI-PM+, " : "", > + (override & PCIE_LINK_STATE_L1_2_PCIPM) ? "L1.2 PCI-PM+" : ""); > + } > +} > + > static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) > { > struct pci_dev *child = link->downstream, *parent = link->pdev; > @@ -868,6 +904,8 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) > /* Save default state */ > link->aspm_default = link->aspm_enabled; > > + pcie_aspm_override_default_link_state(link); > + > /* Setup initial capable state. Will be updated later */ > link->aspm_capable = link->aspm_support; Since this commit was added in Linux v6.18, I have been observing a suspend test failures on some of our boards. The suspend test suspends the devices for 20 secs and before this change the board would resume in about ~27 secs (including the 20 sec sleep). After this change the board would take over 80 secs to resume and this triggered a failure. Looking at the logs, I can see it is the NVMe device on the board that is having an issue, and I see the reset failing ... [ 945.754939] r8169 0007:01:00.0 enP7p1s0: Link is Up - 1Gbps/Full - flow control rx/tx [ 1002.467432] nvme nvme0: I/O tag 12 (400c) opcode 0x9 (Admin Cmd) QID 0 timeout, reset controller [ 1002.493713] nvme nvme0: 12/0/0 default/read/poll queues [ 1003.050448] nvme nvme0: ctrl state 1 is not RESETTING [ 1003.050481] OOM killer enabled. [ 1003.054035] nvme nvme0: Disabling device after reset failure: -19 From the above timestamps the delay is coming from the NVMe. I see this issue on several boards with different NVMe devices and I can workaround this by disabling ASPM L0/L1 for these devices ... DECLARE_PCI_FIXUP_HEADER(0x15b7, 0x5011, quirk_disable_aspm_l0s_l1); DECLARE_PCI_FIXUP_HEADER(0x15b7, 0x5036, quirk_disable_aspm_l0s_l1); DECLARE_PCI_FIXUP_HEADER(0x1b4b, 0x1322, quirk_disable_aspm_l0s_l1); DECLARE_PCI_FIXUP_HEADER(0xc0a9, 0x540a, quirk_disable_aspm_l0s_l1); I am curious if you have seen any similar issues? Other PCIe devices seem to be OK (like the realtek r8169) but just the NVMe is having issues. So I am trying to figure out the best way to resolve this? Thanks Jon -- nvpublic