From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
To: Jim Quinlan <james.quinlan@broadcom.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Rob Herring <robh@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Florian Fainelli <f.fainelli@gmail.com>,
"maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE"
<bcm-kernel-feedback-list@broadcom.com>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-rpi-kernel@lists.infradead.org>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
"open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS"
<linux-pci@vger.kernel.org>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 04/15] PCI: brcmstb: Add compatibily of other chips
Date: Fri, 22 May 2020 11:17:08 +0200 [thread overview]
Message-ID: <75a1dd87d18103f1e8b0afbd1e0718c74c4a77d4.camel@suse.de> (raw)
In-Reply-To: <CA+-6iNyqtFguHJ=sB=nKoghX6PR9ve5OuyafPw88mfSmhe+c8Q@mail.gmail.com>
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On Thu, 2020-05-21 at 15:35 -0400, Jim Quinlan wrote:
> On Wed, May 20, 2020 at 7:51 AM Nicolas Saenz Julienne
[...]
> > > /*
> > > @@ -602,20 +667,21 @@ static struct pci_ops brcm_pcie_ops = {
> > >
> > > static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie,
> > > u32
> > > val)
> > > {
> > > - u32 tmp;
> > > + u32 tmp, mask = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK];
> > > + u32 shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT];
> >
> > I don't think you need shift here, IIUC u32p_replace_bits() will take care
> > of
> > all the masking and shifting internally, moreover, you'd be able to drop the
> > shift entry from reg_field_info.
> I believe that u32p_replace_bits requires at least one of the value or
> mask to be compile time constants to work and we don't have that here.
Of course, sorry for the noise then.
Regards,
Nicolas
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next prev parent reply other threads:[~2020-05-22 9:17 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-19 20:33 [PATCH 00/15] PCI: brcmstb: enable PCIe for STB chips Jim Quinlan
2020-05-19 20:33 ` [PATCH 01/15] PCI: brcmstb: PCIE_BRCMSTB depends on ARCH_BRCMSTB Jim Quinlan
2020-05-19 20:48 ` Florian Fainelli
2020-05-19 20:34 ` [PATCH 03/15] dt-bindings: PCI: Add bindings for more Brcmstb chips Jim Quinlan
2020-05-19 20:34 ` [PATCH 04/15] PCI: brcmstb: Add compatibily of other chips Jim Quinlan
2020-05-20 11:51 ` Nicolas Saenz Julienne
2020-05-20 14:30 ` Jim Quinlan
2020-05-20 14:41 ` Nicolas Saenz Julienne
2020-05-21 19:35 ` Jim Quinlan
2020-05-22 9:17 ` Nicolas Saenz Julienne [this message]
2020-05-19 20:34 ` [PATCH 05/15] PCI: brcmstb: Add suspend and resume pm_ops Jim Quinlan
2020-05-19 20:34 ` [PATCH 06/15] PCI: brcmstb: Asserting PERST is different for 7278 Jim Quinlan
2020-05-19 20:34 ` [PATCH 07/15] PCI: brcmstb: Add control of rescal reset Jim Quinlan
2020-05-20 7:27 ` Philipp Zabel
2020-05-21 21:48 ` Jim Quinlan
2020-05-25 16:58 ` Florian Fainelli
2020-05-19 20:34 ` [PATCH 12/15] PCI: brcmstb: Set internal memory viewport sizes Jim Quinlan
2020-05-19 20:34 ` [PATCH 13/15] PCI: brcmstb: Accommodate MSI for older chips Jim Quinlan
2020-05-19 20:34 ` [PATCH 14/15] PCI: brcmstb: Set bus max burst side by chip type Jim Quinlan
2020-05-20 13:44 ` Nicolas Saenz Julienne
2020-05-20 14:27 ` Jim Quinlan
2020-05-19 20:34 ` [PATCH 15/15] PCI: brcmstb: add compatilbe chips to match list Jim Quinlan
2020-05-20 16:15 ` [PATCH 00/15] PCI: brcmstb: enable PCIe for STB chips Bjorn Helgaas
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