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Date: Fri, 30 May 2025 19:24:53 +0200
From: Niklas Cassel <cassel@kernel.org>
To: Bjorn Helgaas <helgaas@kernel.org>,
 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
CC: Lorenzo Pieralisi <lpieralisi@kernel.org>,
 =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= <kw@linux.com>,
 Rob Herring <robh@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>,
 Heiko Stuebner <heiko@sntech.de>, Wilfred Mallawa <wilfred.mallawa@wdc.com>,
 Damien Le Moal <dlemoal@kernel.org>, Hans Zhang <18255117159@163.com>,
 Laszlo Fiat <laszlo.fiat@proton.me>,
 =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= <kwilczynski@kernel.org>,
 linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
 linux-rockchip@lists.infradead.org
Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v2_1/4=5D_PCI=3A_dw-rockchip=3A_Do_not_e?=
 =?US-ASCII?Q?numerate_bus_before_endpoint_devices_are_ready?=
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On 30 May 2025 19:19:37 CEST, Bjorn Helgaas <helgaas@kernel=2Eorg> wrote:
>
>I think all drivers should wait PCIE_T_RRS_READY_MS (100ms) after exit
>from Conventional Reset (if port only supports <=3D 5=2E0 GT/s) or after
>link training completes (if port supports > 5=2E0 GT/s)=2E
>
>> So I don't think this is a device specific issue but rather
>> controller specific=2E  And this makes the Qcom patch that I dropped a
>> valid one (ofc with change in description)=2E
>
>URL?

PATCH 4/4 of this series=2E


Kind regards,
Niklas