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X-CSE-ConnectionGUID: p6xkbeNTTASSPilCAZJxcQ== X-CSE-MsgGUID: U/1jBsdeQwiT0niigd1t/g== X-IronPort-AV: E=McAfee;i="6800,10657,11805"; a="81250059" X-IronPort-AV: E=Sophos;i="6.24,183,1774335600"; d="scan'208";a="81250059" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2026 11:12:44 -0700 X-CSE-ConnectionGUID: pmgZQr/0ST66+Q6hWzO60Q== X-CSE-MsgGUID: P3AgbKtIRZ+ufTqBgJiT+A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,183,1774335600"; d="scan'208";a="243135761" Received: from rchatre-mobl4.amr.corp.intel.com (HELO [10.125.108.56]) ([10.125.108.56]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2026 11:12:43 -0700 Message-ID: <79fbf3fc-81ce-45c3-9889-be4c3867bfb8@intel.com> Date: Tue, 2 Jun 2026 11:12:42 -0700 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 1/9] cxl/hdm: Add helpers to restore and commit memdev decoders To: Richard Cheng , Srirangan Madhavan Cc: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, vsethi@nvidia.com, alwilliamson@nvidia.com, Dan Williams , Sai Yashwanth Reddy Kancherla , Vishal Aslot , Manish Honap , Jiandi An , linux-tegra@vger.kernel.org References: <20260528083154.137979-1-smadhavan@nvidia.com> <20260528083154.137979-2-smadhavan@nvidia.com> Content-Language: en-US From: Dave Jiang In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 5/28/26 4:06 AM, Richard Cheng wrote: > On Thu, May 28, 2026 at 08:31:46AM +0800, Srirangan Madhavan wrote: <-- snip --> >> +static int cxl_restore_dvsec_range(struct cxl_memdev *cxlmd, >> + struct cxl_endpoint_decoder *cxled) >> +{ >> + struct cxl_dev_state *cxlds = cxlmd->cxlds; >> + struct cxl_decoder *cxld = &cxled->cxld; >> + struct pci_dev *pdev = to_pci_dev(cxlds->dev); >> + u64 base = cxld->hpa_range.start; >> + u64 size = range_len(&cxld->hpa_range); >> + u32 lo; >> + int dvsec = cxlds->cxl_dvsec; >> + int id = cxld->id; >> + int rc; >> + >> + if (!dvsec) >> + return 0; >> + >> + if (id >= CXL_DVSEC_RANGE_MAX) >> + return 0; >> + >> + rc = pci_write_config_dword(pdev, dvsec + PCI_DVSEC_CXL_RANGE_BASE_HIGH(id), >> + upper_32_bits(base)); >> + if (rc) >> + return rc; >> + >> + rc = pci_read_config_dword(pdev, dvsec + PCI_DVSEC_CXL_RANGE_BASE_LOW(id), >> + &lo); >> + if (rc) >> + return rc; > > Here pci_read/write* returns positive values on failure, and you pass the value up. > Eventually surfacing through cxl_reset_store to userspace where sysfs thinks positive > values as "bytes written". > > I think this might need a fix ? Great catch! Not something I ever thought about before WRT pci_read/write*. I think to get errno it needs pcibios_err_to_errno() wrapper called. The sysfs exposure definitely needs to be audited.