From: Mohit Kumar <mohit.kumar@st.com>
To: <linux-pci@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>
Cc: Pratyush Anand <pratyush.anand@st.com>,
Mohit Kumar <mohit.kumar@st.com>,
Jingoo Han <jg1.han@samsung.com>, <spear-devel@list.st.com>
Subject: [PATCH 06/12] pcie: designware: Move register definition to the header file
Date: Wed, 11 Dec 2013 15:08:31 +0530 [thread overview]
Message-ID: <7bce26f60d847a136f748b5eeac15dc79a7d662e.1386752447.git.mohit.kumar@st.com> (raw)
In-Reply-To: <cover.1386752447.git.mohit.kumar@st.com>
From: Pratyush Anand <pratyush.anand@st.com>
Move synopsis specific register definition from source file to header
file, so that they can be re-used by other files if needed.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: spear-devel@list.st.com
Cc: linux-pci@vger.kernel.org
---
drivers/pci/host/pcie-designware.c | 42 ------------------------------------
drivers/pci/host/pcie-designware.h | 42 ++++++++++++++++++++++++++++++++++++
2 files changed, 42 insertions(+), 42 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 212b8b6..73aa13c 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -23,48 +23,6 @@
#include "pcie-designware.h"
-/* Synopsis specific PCIE configuration registers */
-#define PCIE_PORT_LINK_CONTROL 0x710
-#define PORT_LINK_MODE_MASK (0x3f << 16)
-#define PORT_LINK_MODE_1_LANES (0x1 << 16)
-#define PORT_LINK_MODE_2_LANES (0x3 << 16)
-#define PORT_LINK_MODE_4_LANES (0x7 << 16)
-
-#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
-#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
-#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
-#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
-#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
-#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
-
-#define PCIE_MSI_ADDR_LO 0x820
-#define PCIE_MSI_ADDR_HI 0x824
-#define PCIE_MSI_INTR0_ENABLE 0x828
-#define PCIE_MSI_INTR0_MASK 0x82C
-#define PCIE_MSI_INTR0_STATUS 0x830
-
-#define PCIE_ATU_VIEWPORT 0x900
-#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
-#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
-#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
-#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
-#define PCIE_ATU_CR1 0x904
-#define PCIE_ATU_TYPE_MEM (0x0 << 0)
-#define PCIE_ATU_TYPE_IO (0x2 << 0)
-#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
-#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
-#define PCIE_ATU_CR2 0x908
-#define PCIE_ATU_ENABLE (0x1 << 31)
-#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
-#define PCIE_ATU_LOWER_BASE 0x90C
-#define PCIE_ATU_UPPER_BASE 0x910
-#define PCIE_ATU_LIMIT 0x914
-#define PCIE_ATU_LOWER_TARGET 0x918
-#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
-#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
-#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
-#define PCIE_ATU_UPPER_TARGET 0x91C
-
static struct hw_pci dw_pci;
static unsigned long global_io_offset;
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index c15379b..da1ed35 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -74,4 +74,46 @@ int dw_pcie_link_up(struct pcie_port *pp);
void dw_pcie_setup_rc(struct pcie_port *pp);
int dw_pcie_host_init(struct pcie_port *pp);
+/* Synopsis specific PCIE configuration registers */
+#define PCIE_PORT_LINK_CONTROL 0x710
+#define PORT_LINK_MODE_MASK (0x3f << 16)
+#define PORT_LINK_MODE_1_LANES (0x1 << 16)
+#define PORT_LINK_MODE_2_LANES (0x3 << 16)
+#define PORT_LINK_MODE_4_LANES (0x7 << 16)
+
+#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
+#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
+#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
+#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
+#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
+#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
+
+#define PCIE_MSI_ADDR_LO 0x820
+#define PCIE_MSI_ADDR_HI 0x824
+#define PCIE_MSI_INTR0_ENABLE 0x828
+#define PCIE_MSI_INTR0_MASK 0x82C
+#define PCIE_MSI_INTR0_STATUS 0x830
+
+#define PCIE_ATU_VIEWPORT 0x900
+#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
+#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
+#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
+#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
+#define PCIE_ATU_CR1 0x904
+#define PCIE_ATU_TYPE_MEM (0x0 << 0)
+#define PCIE_ATU_TYPE_IO (0x2 << 0)
+#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
+#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
+#define PCIE_ATU_CR2 0x908
+#define PCIE_ATU_ENABLE (0x1 << 31)
+#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
+#define PCIE_ATU_LOWER_BASE 0x90C
+#define PCIE_ATU_UPPER_BASE 0x910
+#define PCIE_ATU_LIMIT 0x914
+#define PCIE_ATU_LOWER_TARGET 0x918
+#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
+#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
+#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
+#define PCIE_ATU_UPPER_TARGET 0x91C
+
#endif /* _PCIE_DESIGNWARE_H */
--
1.7.0.1
next prev parent reply other threads:[~2013-12-11 10:08 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-11 9:38 [PATCH 00/12] PCI:Add SPEAr13xx PCie support Mohit Kumar
2013-12-11 9:38 ` [PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy-addr Mohit Kumar
2013-12-11 11:09 ` Rajeev kumar
2013-12-11 11:14 ` Rajeev kumar
2013-12-12 0:39 ` Jingoo Han
2013-12-12 3:59 ` Rajeev kumar
2013-12-12 4:07 ` Chen-Yu Tsai
2013-12-12 5:13 ` Mohit KUMAR DCG
2013-12-11 9:38 ` [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header file Mohit Kumar
2013-12-11 22:48 ` Arnd Bergmann
2013-12-13 4:18 ` Mohit KUMAR DCG
2013-12-14 19:02 ` Arnd Bergmann
2014-01-16 7:25 ` Mohit KUMAR DCG
2014-01-16 9:19 ` Pratyush Anand
2014-01-16 11:33 ` Arnd Bergmann
2014-01-16 11:45 ` Pratyush Anand
2013-12-11 9:38 ` [PATCH 03/12] SPEAr13xx: Add SPEAr1310 PCIe register definitions Mohit Kumar
2013-12-11 22:51 ` Arnd Bergmann
2013-12-11 9:38 ` [PATCH 04/12] SPEAr13xx: Fix static mapping table Mohit Kumar
2013-12-11 9:38 ` [PATCH 05/12] clk: SPEAr13xx: Fix pcie clock name Mohit Kumar
2013-12-11 22:42 ` Arnd Bergmann
2013-12-12 5:00 ` Mohit KUMAR DCG
2013-12-12 21:30 ` Arnd Bergmann
2013-12-11 9:38 ` Mohit Kumar [this message]
2013-12-11 11:38 ` [PATCH 06/12] pcie: designware: Move register definition to the header file Jagan Teki
2013-12-11 11:55 ` Mohit KUMAR DCG
2013-12-11 12:04 ` Jagan Teki
2013-12-11 21:31 ` Arnd Bergmann
2013-12-11 22:48 ` Jingoo Han
2013-12-12 4:55 ` Mohit KUMAR DCG
2013-12-11 9:38 ` [PATCH 07/12] pcie: designware: add dw_pcie prefix before cfg_read/write Mohit Kumar
2013-12-11 11:40 ` Jagan Teki
2013-12-12 1:12 ` Jingoo Han
2013-12-12 1:05 ` Jingoo Han
2013-12-20 16:35 ` Bjorn Helgaas
2013-12-11 9:38 ` [PATCH 08/12] pcie: designware: Fix IO transfers Mohit Kumar
2013-12-11 10:03 ` Marek Vasut
2013-12-11 11:29 ` Jagan Teki
2013-12-12 1:17 ` Jingoo Han
2013-12-20 3:47 ` Pratyush Anand
2013-12-11 13:34 ` Arnd Bergmann
2013-12-11 23:34 ` Jingoo Han
2013-12-20 16:36 ` Bjorn Helgaas
2013-12-11 9:38 ` [PATCH 09/12] pcie: SPEAr13xx: Add designware pcie support Mohit Kumar
2013-12-11 23:00 ` Arnd Bergmann
2013-12-13 4:30 ` Mohit KUMAR DCG
2013-12-13 4:57 ` Jingoo Han
2013-12-14 19:01 ` Arnd Bergmann
2013-12-11 9:38 ` [PATCH 10/12] SPEAr13xx: defconfig: Update Mohit Kumar
2013-12-11 10:47 ` Rajeev kumar
2013-12-12 4:47 ` Mohit KUMAR DCG
2013-12-11 9:38 ` [PATCH 11/12] MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer Mohit Kumar
2013-12-12 1:55 ` Jingoo Han
2013-12-11 9:38 ` [PATCH 12/12] MAINTAINERS: Add Synopsis Designware " Mohit Kumar
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