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Tue, 08 Jul 2025 03:09:57 -0700 (PDT) Received: from [192.168.50.4] ([82.78.167.30]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae3f66d931csm875767566b.10.2025.07.08.03.09.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 08 Jul 2025 03:09:57 -0700 (PDT) Message-ID: <7c8c7a25-c373-452a-9fe8-8b2d92ddd885@tuxon.dev> Date: Tue, 8 Jul 2025 13:09:55 +0300 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 7/9] arm64: dts: renesas: rzg3s-smarc-som: Update dma-ranges for PCIe To: Biju Das , "bhelgaas@google.com" , "lpieralisi@kernel.org" , "kwilczynski@kernel.org" , "mani@kernel.org" , "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , "geert+renesas@glider.be" , "magnus.damm@gmail.com" , "catalin.marinas@arm.com" , "will@kernel.org" , "mturquette@baylibre.com" , "sboyd@kernel.org" , "p.zabel@pengutronix.de" , "lizhi.hou@amd.com" Cc: "linux-pci@vger.kernel.org" , "linux-renesas-soc@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-clk@vger.kernel.org" , Claudiu Beznea , Wolfram Sang References: <20250704161410.3931884-1-claudiu.beznea.uj@bp.renesas.com> <20250704161410.3931884-8-claudiu.beznea.uj@bp.renesas.com> From: Claudiu Beznea Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi, Biju, On 07.07.2025 11:18, Biju Das wrote: > Hi Claudiu, > >> -----Original Message----- >> From: Claudiu >> Sent: 04 July 2025 17:14 >> Subject: [PATCH v3 7/9] arm64: dts: renesas: rzg3s-smarc-som: Update dma-ranges for PCIe >> >> From: Claudiu Beznea >> >> The first 128MB of memory is reserved on this board for secure area. >> Update the PCIe dma-ranges property to reflect this. > > I see R-Car PCIe dma-ranges[1] and [2] maps all possible DDR area supported by the SoC? > Do we need to make board specific as well there? I'm not familiar with R-Car, but if there are ranges reserved for other purposes, I think we should reflect it in board specific device trees. But that would have to be address though a different series as it has nothing to do with enabling the RZ/G3S PCIe support. Thank you, Claudiu > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r8a774e1.dtsi?h=next-20250704#n2487 > [2] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/salvator-common.dtsi?h=next-20250704 > > Cheers, > Biju > >> >> Tested-by: Wolfram Sang >> Signed-off-by: Claudiu Beznea >> --- >> >> Changes in v3: >> - collected tags >> >> Changes in v2: >> - none, this patch is new >> >> arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s- >> smarc-som.dtsi >> index 39845faec894..1b03820a6f02 100644 >> --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi >> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi >> @@ -214,6 +214,11 @@ &sdhi2 { >> }; >> #endif >> >> +&pcie { >> + /* First 128MB is reserved for secure area. */ >> + dma-ranges = <0x42000000 0 0x48000000 0 0x48000000 0x0 0x38000000>; }; >> + >> &pinctrl { >> #if SW_CONFIG3 == SW_ON >> eth0-phy-irq-hog { >> -- >> 2.43.0 >> >