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Wed, 28 Feb 2024 13:07:12 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41SD7B9i026071 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 28 Feb 2024 13:07:11 GMT Received: from [10.218.10.86] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 28 Feb 2024 05:07:04 -0800 Message-ID: <7cd328e2-6847-973f-c38b-93d1e64d3771@quicinc.com> Date: Wed, 28 Feb 2024 18:37:01 +0530 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH v5 0/3] arm64: qcom: sa8775p: add cache coherency support for SA8775P Content-Language: en-US To: Krzysztof Kozlowski , , , , , , CC: , , , , , , , , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Bjorn Helgaas , , , , References: <1708697021-16877-1-git-send-email-quic_msarkar@quicinc.com> <866ea7ee-54c3-4a89-981e-64d6d3b46497@linaro.org> From: Mrinmay Sarkar In-Reply-To: <866ea7ee-54c3-4a89-981e-64d6d3b46497@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: HCcCySSSp6hMcYQVt0MSg1qXLvCNmev2 X-Proofpoint-ORIG-GUID: HCcCySSSp6hMcYQVt0MSg1qXLvCNmev2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-28_06,2024-02-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 spamscore=0 mlxlogscore=954 lowpriorityscore=0 mlxscore=0 bulkscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2402280103 On 2/24/2024 3:49 PM, Krzysztof Kozlowski wrote: > On 23/02/2024 15:03, Mrinmay Sarkar wrote: >> Due to some hardware changes, SA8775P has set the NO_SNOOP attribute >> in its TLP for all the PCIe controllers. NO_SNOOP attribute when set, >> the requester is indicating that there no cache coherency issues exit >> for the addressed memory on the host i.e., memory is not cached. But >> in reality, requester cannot assume this unless there is a complete >> control/visibility over the addressed memory on the host. >> >> And worst case, if the memory is cached on the host, it may lead to >> memory corruption issues. It should be noted that the caching of memory >> on the host is not solely dependent on the NO_SNOOP attribute in TLP. >> >> So to avoid the corruption, this patch overrides the NO_SNOOP attribute >> by setting the PCIE_PARF_NO_SNOOP_OVERIDE register. This patch is not >> needed for other upstream supported platforms since they do not set >> NO_SNOOP attribute by default. >> >> This series is to enable cache snooping logic in both RC and EP driver >> and add the "dma-coherent" property in dtsi to support cache coherency >> in SA8775P platform. > Please confirm that your patchset passes 100% dtbs_check. > > Best regards, > Krzysztof I have run dtbs_check and it is passing. Thanks Mrinmay >