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([2a00:1fa0:469c:53c3:78a2:dd7e:1a3c:8259]) by smtp.gmail.com with ESMTPSA id l29sm2359183lfp.11.2020.09.27.01.29.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 27 Sep 2020 01:29:28 -0700 (PDT) Subject: Re: [PATCH V2] PCI: rcar: Add L1 link state fix into data abort hook To: marek.vasut@gmail.com, linux-pci@vger.kernel.org Cc: Marek Vasut , Bjorn Helgaas , Geert Uytterhoeven , Lorenzo Pieralisi , Wolfram Sang , Yoshihiro Shimoda , linux-renesas-soc@vger.kernel.org References: <20200926160934.136182-1-marek.vasut@gmail.com> From: Sergei Shtylyov Organization: Brain-dead Software Message-ID: <7ce58972-2946-0107-2298-c5a6f6e12feb@gmail.com> Date: Sun, 27 Sep 2020 11:29:23 +0300 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <20200926160934.136182-1-marek.vasut@gmail.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Hello! On 26.09.2020 19:09, marek.vasut@gmail.com wrote: > From: Marek Vasut > > The R-Car PCIe controller is capable of handling L0s/L1 link states. > While the controller can enter and exit L0s link state, and exit L1 > link state, without any additional action from the driver, to enter > L1 link state, the driver must complete the link state transition by > issuing additional commands to the controller. > > The problem is, this transition is not atomic. The controller sets > PMEL1RX bit in PMSR register upon reception of PM_ENTER_L1 DLLP from > the PCIe card, but then the controller enters some sort of inbetween > state. The driver must detect this condition and complete the link > state transition, by setting L1IATN bit in PMCTLR and waiting for > the link state transition to complete. > > If a PCIe access happens inside of this window, where the controller s/of//. > is inbetween L0 and L1 link states, the access generates a fault and My spellchecker trips on "inbetween"... > the ARM 'imprecise external abort' handler is invoked. > > Just like other PCI controller drivers, here we hook the fault handler, > perform the fixup to help the controller enter L1 link state, and then > restart the instruction which triggered the fault. Since the controller If this is imprecise or async external abort, how we can re-execute the instruction that triggered the fault? It's been probably executed already, no? > is in L1 link state now, the link can exit from L1 link state to L0 and > successfully complete the access. > > Note that this fixup is applicable only to Aarch32 R-Car controllers, > the Aarch64 R-Car perform the same fixup in TFA, see TFA commit [1] > 0969397f2 ("rcar_gen3: plat: Prevent PCIe hang during L1X config access") > [1] https://github.com/ARM-software/arm-trusted-firmware/commit/0969397f295621aa26b3d14b76dd397d22be58bf > > Signed-off-by: Marek Vasut > Cc: Bjorn Helgaas > Cc: Geert Uytterhoeven > Cc: Lorenzo Pieralisi > Cc: Wolfram Sang > Cc: Yoshihiro Shimoda > Cc: linux-renesas-soc@vger.kernel.org [...] > +static int __init rcar_pcie_init(void) > +{ > +#ifdef CONFIG_ARM_LPAE > + hook_fault_code(17, rcar_pcie_aarch32_abort_handler, SIGBUS, 0, > + "asynchronous external abort"); > +#else > + hook_fault_code(22, rcar_pcie_aarch32_abort_handler, SIGBUS, 0, > + "imprecise external abort"); > +#endif > + return platform_driver_register(&rcar_pcie_driver); > +} > +device_initcall(rcar_pcie_init); > +#else > builtin_platform_driver(rcar_pcie_driver); > +#endif [...] MBR, Sergei