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Sun, 19 Nov 2023 17:10:59 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.9.0-alpha0-1108-g3a29173c6d-fm-20231031.005-g3a29173c MIME-Version: 1.0 Message-Id: <7d094389-64ff-40d5-8918-b79ef4f62986@app.fastmail.com> In-Reply-To: <20231119215635.52810-1-jiaxun.yang@flygoat.com> References: <20231119215635.52810-1-jiaxun.yang@flygoat.com> Date: Sun, 19 Nov 2023 22:10:39 +0000 From: "Jiaxun Yang" To: linux-pci Cc: "Lorenzo Pieralisi" , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , "Rob Herring" , linux-kernel@vger.kernel.org, "Huacai Chen" , "stable@vger.kernel.org" Subject: Re: [PATCH v5] pci: loongson: Workaround MIPS firmware MRRS settings Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org =E5=9C=A82023=E5=B9=B411=E6=9C=8819=E6=97=A5=E5=8D=81=E4=B8=80=E6=9C=88 = =E4=B8=8B=E5=8D=889:56=EF=BC=8CJiaxun Yang=E5=86=99=E9=81=93=EF=BC=9A > This is a partial revert of commit 8b3517f88ff2 ("PCI: > loongson: Prevent LS7A MRRS increases") for MIPS based Loongson. > > There are many MIPS based Loongson systems in wild that > shipped with firmware which does not set maximum MRRS properly. > > Limiting MRRS to 256 for all as MIPS Loongson comes with higher > MRRS support is considered rare. > > It must be done at device enablement stage because MRRS setting > may get lost if the parent bridge lost PCI_COMMAND_MASTER, and > we are only sure parent bridge is enabled at this point. > > Cc: stable@vger.kernel.org > Closes: https://bugzilla.kernel.org/show_bug.cgi?id=3D217680 > Fixes: 8b3517f88ff2 ("PCI: loongson: Prevent LS7A MRRS increases") > Signed-off-by: Jiaxun Yang > --- > v4: Improve commit message > v5: > - Improve commit message and comments. > - Style fix from Huacai's off-list input. > --- > drivers/pci/controller/pci-loongson.c | 47 ++++++++++++++++++++++++--- > 1 file changed, 42 insertions(+), 5 deletions(-) > > diff --git a/drivers/pci/controller/pci-loongson.c=20 > b/drivers/pci/controller/pci-loongson.c > index d45e7b8dc530..128cc95b236f 100644 > --- a/drivers/pci/controller/pci-loongson.c > +++ b/drivers/pci/controller/pci-loongson.c > @@ -80,13 +80,50 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > DEV_LS7A_LPC, system_bus_quirk); >=20 > +/* > + * Some Loongson PCIe ports have h/w limitations of maximum read > + * request size. They can't handle anything larger than this. > + * Sane firmware will set proper MRRS at boot, so we only need > + * no_inc_mrrs for bridges. However, some MIPS Loongson firmware > + * won't set MRRS properly, and we have to enforce maximum safe > + * MRRS, which is 256 bytes. > + */ > +#ifdef CONFIG_MIPS > +static void loongson_set_min_mrrs_quirk(struct pci_dev *pdev) > +{ > + struct pci_bus *bus =3D pdev->bus; > + struct pci_dev *bridge; > + static const struct pci_device_id bridge_devids[] =3D { > + { PCI_VDEVICE(LOONGSON, DEV_LS2K_PCIE_PORT0) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT0) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT1) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT2) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT3) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT4) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT5) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT6) }, > + { 0, }, > + }; > + > + /* look for the matching bridge */ > + while (!pci_is_root_bus(bus)) { > + bridge =3D bus->self; > + bus =3D bus->parent; > + > + if (pci_match_id(bridge_devids, bridge)) { > + if (pcie_get_readrq(pdev) > 256) { > + pci_info(pdev, "limiting MRRS to 256\n"); > + pcie_set_readrq(pdev, 256); > + } > + break; > + } > + } > +} > +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk_= old); ^ Oops sed issue. Will fix in next version if everybody is happy with the implementation. Thanks --=20 - Jiaxun