From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95E511D52D; Fri, 23 Aug 2024 04:29:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724387377; cv=none; b=SDyP4sWi6VjUt3m/iII2PDyTkhrPZBPLtD41J5IuV3JPK0Vaad03TL9C507QYgQ6b7ArKXVtb2BKqMpeNvGE9mwxyWaGl75NnDIW4xCISnu4WnCa+nBXrXThiUiq+H40aKqT5GBXxCh7/yNzDmZDQIdZr/HdaKgaq6AH/TxP/Lg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724387377; c=relaxed/simple; bh=UXfub7lxWQQk708n0yCS+LPs/EwBWlEj884ZhFNBNCU=; h=Message-ID:Date:MIME-Version:Subject:From:To:Cc:References: In-Reply-To:Content-Type; b=bwNN9Z9u1808leDwUl8qD070p6GxT+mspOcwOmSIpp51Nu2/2PL7oeXn5YTDwT7chYU95iU3DoChQY/C5rfNnRNbkoj8KnMfdJqf9VoqJFQD1Fnsoq8Jcj4Dv4WQcGj8oxTXZqm+iy1KHJKEHE10968bmr1HidGRG0kC4qnODVw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QCy+FjUp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QCy+FjUp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 20EB3C32786; Fri, 23 Aug 2024 04:29:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724387377; bh=UXfub7lxWQQk708n0yCS+LPs/EwBWlEj884ZhFNBNCU=; h=Date:Subject:From:To:Cc:References:In-Reply-To:From; b=QCy+FjUpqUv5OefnMvK/eNcAFXs2SRCtn13IGn3+VQe156jIinbaLugAAHjSqiG3K qG0/Ptc3dFJGCOspwTmxQ11se+dZ7piWLTVr0hXW3eR9uKvHzruNq91ZowXFQeltPN cVRK7Oc9Y83E2ohJ7z0Iy+69E3Hu7UuCx28KBXDEVOO61mkUJ/WUjRXLLRu5KHwBna oMFPhGhgfV6tDejdYNBgEZGA5ATEE2A+Hg2HczM7zRYwUc1j+FvyQ8Ex0u5gyEuAv4 BLvQ29qdUnu1g0iBzKnKYMWzJtF/6o8hZk1c+8df7B8scuvTo65HqS0oqdPNdU8A9Z Z6SxRSZB3aXUQ== Message-ID: <80132627-5585-456b-a8b3-788d83808d3b@kernel.org> Date: Thu, 22 Aug 2024 23:29:33 -0500 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] x86/tsc: Use rdtsc_ordered() when RDTSCP or LFENCE_RDTSC are supported From: Mario Limonciello To: Bjorn Helgaas , Mathias Nyman , Mika Westerberg Cc: "open list : PCI SUBSYSTEM" , open list , "open list : USB XHCI DRIVER" , Daniel Drake , Gary Li , Greg Kroah-Hartman , =?UTF-8?Q?Ilpo_J=C3=A4rvinen?= , Mario Limonciello References: <20240823042508.1057791-1-superm1@kernel.org> <20240823042508.1057791-3-superm1@kernel.org> Content-Language: en-US In-Reply-To: <20240823042508.1057791-3-superm1@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 8/22/24 23:25, Mario Limonciello wrote: > From: Mario Limonciello > > On AMD processors the TSC has been reported drifting on and off for > various platforms. This has been root caused to becaused by out of order > TSC and HPET counter values. When the SoC supports RDTSCP or LFENCE_RDTSC > use ordered tsc reads instead. > > Signed-off-by: Mario Limonciello > --- > arch/x86/include/asm/tsc.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h > index 94408a784c8e7..1c0cda1702bec 100644 > --- a/arch/x86/include/asm/tsc.h > +++ b/arch/x86/include/asm/tsc.h > @@ -24,6 +24,9 @@ static inline cycles_t get_cycles(void) > if (!IS_ENABLED(CONFIG_X86_TSC) && > !cpu_feature_enabled(X86_FEATURE_TSC)) > return 0; > + if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC) || > + cpu_feature_enabled(X86_FEATURE_RDTSCP)) > + return rdtsc_ordered(); > return rdtsc(); > } > #define get_cycles get_cycles Sorry; this unrelated patch I didn't intend to include in the series, it was in my working directory by accident. Please disregard it for now, but review the rest of the series. Thanks!