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From: "Jianjun Wang (王建军)" <Jianjun.Wang@mediatek.com>
To: "manivannan.sadhasivam@linaro.org"
	<manivannan.sadhasivam@linaro.org>,
	"conor+dt@kernel.org" <conor+dt@kernel.org>,
	"robh@kernel.org" <robh@kernel.org>,
	"kw@linux.com" <kw@linux.com>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>,
	"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
	"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
	AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>
Cc: "linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-mediatek@lists.infradead.org"
	<linux-mediatek@lists.infradead.org>,
	"Ryder Lee" <Ryder.Lee@mediatek.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"Xavier Chang (張獻文)" <Xavier.Chang@mediatek.com>
Subject: Re: [PATCH 1/5] dt-bindings: PCI: mediatek-gen3: Add MT8196 support
Date: Mon, 6 Jan 2025 09:19:26 +0000	[thread overview]
Message-ID: <8269f5fb280d0847ceba288a83a64c99bbf92cb7.camel@mediatek.com> (raw)
In-Reply-To: <0555fb64-312d-4490-9b03-89fca580c602@collabora.com>

On Fri, 2025-01-03 at 10:26 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> Il 03/01/25 07:00, Jianjun Wang ha scritto:
> > Add compatible string and clock definition for MT8196. It has 6
> > clocks like
> > the MT8195, but 2 of them are different.
> > 
> > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> > ---
> >   .../bindings/pci/mediatek-pcie-gen3.yaml      | 29
> > +++++++++++++++++++
> >   1 file changed, 29 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-
> > gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-
> > gen3.yaml
> > index f05aab2b1add..b4158a666fb6 100644
> > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > @@ -51,6 +51,7 @@ properties:
> >                 - mediatek,mt7986-pcie
> >                 - mediatek,mt8188-pcie
> >                 - mediatek,mt8195-pcie
> > +              - mediatek,mt8196-pcie
> >             - const: mediatek,mt8192-pcie
> >         - const: mediatek,mt8192-pcie
> >         - const: airoha,en7581-pcie
> > @@ -197,6 +198,34 @@ allOf:
> >             minItems: 1
> >             maxItems: 2
> > 
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - mediatek,mt8196-pcie
> > +    then:
> > +      properties:
> > +        clocks:
> > +          minItems: 6
> > +
> > +        clock-names:
> > +          items:
> > +            - const: pl_250m
> > +            - const: tl_26m
> > +            - const: peri_26m
> > +            - const: peri_mem
> > +            - const: ahb_apb
> 
> ahb_apb is a bus clock, so you can set it as
> 
> - const: bus

Agree, I'll change it to "bus" in the next version, thanks.

> 
> 
> > +            - const: low_power
> 
> Can you please clarify what the LP clock is for?

This is a power-saving clock. Its clock source consumes less power than
a regular clock, we need to keep this clock on if when entering L1.2
during suspend.

Thanks.

> 
> Thanks,
> Angelo
> 
> > +
> > +        resets:
> > +          minItems: 1
> > +          maxItems: 2
> > +
> > +        reset-names:
> > +          minItems: 1
> > +          maxItems: 2
> > +
> >     - if:
> >         properties:
> >           compatible:
> 
> 

  reply	other threads:[~2025-01-06  9:19 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-03  6:00 [PATCH 0/5] PCI: mediatek-gen3: Add MT8196 support Jianjun Wang
2025-01-03  6:00 ` [PATCH 1/5] dt-bindings: " Jianjun Wang
2025-01-03  9:10   ` Krzysztof Kozlowski
2025-01-06  9:26     ` Jianjun Wang (王建军)
2025-01-06 12:27       ` Krzysztof Kozlowski
2025-01-07  8:43         ` Jianjun Wang (王建军)
2025-01-07  9:02           ` Chen-Yu Tsai
2025-01-08  6:53             ` Jianjun Wang (王建军)
2025-01-08  7:16           ` Krzysztof Kozlowski
2025-01-08  7:30             ` Jianjun Wang (王建军)
2025-01-03  9:26   ` AngeloGioacchino Del Regno
2025-01-06  9:19     ` Jianjun Wang (王建军) [this message]
2025-01-07 13:04       ` AngeloGioacchino Del Regno
2025-01-08  7:24         ` Jianjun Wang (王建军)
2025-01-03  6:00 ` [PATCH 2/5] " Jianjun Wang
2025-01-03 19:02   ` Bjorn Helgaas
2025-01-07  1:51     ` Jianjun Wang (王建军)
2025-01-03  6:00 ` [PATCH 3/5] PCI: mediatek-gen3: Disable ASPM L0s Jianjun Wang
2025-01-03  9:16   ` AngeloGioacchino Del Regno
2025-01-07  2:18     ` Jianjun Wang (王建军)
2025-01-07 11:44       ` AngeloGioacchino Del Regno
2025-01-07 23:07         ` Bjorn Helgaas
2025-01-03 19:15   ` Bjorn Helgaas
2025-01-07  2:44     ` Jianjun Wang (王建军)
2025-01-07 23:06       ` Bjorn Helgaas
2025-01-06 16:09   ` Manivannan Sadhasivam
2025-01-03  6:00 ` [PATCH 4/5] PCI: mediatek-gen3: Don't reply AXI slave error Jianjun Wang
2025-01-03  9:29   ` AngeloGioacchino Del Regno
2025-01-06  9:27     ` Jianjun Wang (王建军)
2025-01-03 19:19   ` Bjorn Helgaas
2025-01-06  9:31     ` Jianjun Wang (王建军)
2025-01-06 16:16   ` Manivannan Sadhasivam
2025-01-07  3:21     ` Jianjun Wang (王建军)
2025-01-03  6:00 ` [PATCH 5/5] PCI: mediatek-gen3: Keep PCIe power and clocks if suspend-to-idle Jianjun Wang
2025-01-03  9:14   ` AngeloGioacchino Del Regno
2025-01-03 19:13   ` Bjorn Helgaas
2025-01-06 16:23   ` Manivannan Sadhasivam

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