From: Jay Cornwall <jay@jcornwall.me>
To: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org
Subject: Re: PCIe 3.0 AtomicOp capabilities
Date: Tue, 11 Aug 2015 19:39:16 -0500 [thread overview]
Message-ID: <841e1480e445f3bcde269a147a269a92@jcornwall.me> (raw)
In-Reply-To: <CAErSpo6OLAjVde8St2kCoqx3h9hX9ki+X9Ojy0eFqugvBKRrwg@mail.gmail.com>
On 2015-08-11 10:10, Bjorn Helgaas wrote:
> On Mon, Aug 10, 2015 at 1:36 PM, Jay Cornwall <jay@jcornwall.me> wrote:
>
>> Should the AtomicOp capabilities be similarly enabled if available? Or
>> might
>> there be a reason for doing this on a per-driver basis?
>
> I'm not very familiar with the AtomicOp functionality, but a quick
> skim of the spec suggests that it does have system implications and
> should be handled by the core. For example, AtomicOp support is
> optional, and it looks like it would be a bad idea to enable it in an
> endpoint if the upstream switch didn't support it.
This makes sense, but I think there are some cases in which upstream is
ambiguous.
For example, consider a root complex which does not support AtomicOp
completion but supports routing to another endpoint which does. Would
the necessary condition for enabling AtomicOp requests be that at least
one other completion-capable endpoint is reachable?
--
Jay Cornwall
next prev parent reply other threads:[~2015-08-12 0:40 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-10 18:36 PCIe 3.0 AtomicOp capabilities Jay Cornwall
2015-08-11 15:10 ` Bjorn Helgaas
2015-08-12 0:39 ` Jay Cornwall [this message]
2015-08-13 20:40 ` Bjorn Helgaas
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