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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Mrinmay Sarkar <quic_msarkar@quicinc.com>,
	andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	conor+dt@kernel.org, konrad.dybcio@linaro.org,
	manivannan.sadhasivam@linaro.org, robh@kernel.org
Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com,
	quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com,
	dmitry.baryshkov@linaro.org, quic_krichai@quicinc.com,
	quic_vbadigan@quicinc.com, quic_schintav@quicinc.com,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v5 0/3] arm64: qcom: sa8775p: add cache coherency support for SA8775P
Date: Sat, 24 Feb 2024 11:19:27 +0100	[thread overview]
Message-ID: <866ea7ee-54c3-4a89-981e-64d6d3b46497@linaro.org> (raw)
In-Reply-To: <1708697021-16877-1-git-send-email-quic_msarkar@quicinc.com>

On 23/02/2024 15:03, Mrinmay Sarkar wrote:
> Due to some hardware changes, SA8775P has set the NO_SNOOP attribute
> in its TLP for all the PCIe controllers. NO_SNOOP attribute when set,
> the requester is indicating that there no cache coherency issues exit
> for the addressed memory on the host i.e., memory is not cached. But
> in reality, requester cannot assume this unless there is a complete
> control/visibility over the addressed memory on the host.
> 
> And worst case, if the memory is cached on the host, it may lead to
> memory corruption issues. It should be noted that the caching of memory
> on the host is not solely dependent on the NO_SNOOP attribute in TLP.
> 
> So to avoid the corruption, this patch overrides the NO_SNOOP attribute
> by setting the PCIE_PARF_NO_SNOOP_OVERIDE register. This patch is not
> needed for other upstream supported platforms since they do not set
> NO_SNOOP attribute by default.
> 
> This series is to enable cache snooping logic in both RC and EP driver
> and add the "dma-coherent" property in dtsi to support cache coherency
> in SA8775P platform.

Please confirm that your patchset passes 100% dtbs_check.

Best regards,
Krzysztof


  parent reply	other threads:[~2024-02-24 10:19 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-23 14:03 [PATCH v5 0/3] arm64: qcom: sa8775p: add cache coherency support for SA8775P Mrinmay Sarkar
2024-02-23 14:03 ` [PATCH v5 1/3] PCI: qcom: Enable cache coherency for SA8775P RC Mrinmay Sarkar
2024-02-23 22:54   ` Bjorn Helgaas
2024-02-28 13:04     ` Mrinmay Sarkar
2024-02-28 15:02       ` Bjorn Helgaas
2024-02-28 17:14         ` Manivannan Sadhasivam
2024-02-28 17:39           ` Bjorn Helgaas
2024-02-28 18:45             ` Manivannan Sadhasivam
2024-02-28 19:34               ` Bjorn Helgaas
2024-03-04  6:00                 ` Manivannan Sadhasivam
2024-03-04  6:07   ` Manivannan Sadhasivam
2024-02-23 14:03 ` [PATCH v5 2/3] PCI: qcom-ep: Enable cache coherency for SA8775P EP Mrinmay Sarkar
2024-02-24  0:07   ` Konrad Dybcio
2024-02-28 13:06     ` Mrinmay Sarkar
2024-02-23 14:03 ` [PATCH v5 3/3] arm64: dts: qcom: sa8775p: Mark PCIe EP controller as cache coherent Mrinmay Sarkar
2024-02-24 10:19 ` Krzysztof Kozlowski [this message]
2024-02-28 13:07   ` [PATCH v5 0/3] arm64: qcom: sa8775p: add cache coherency support for SA8775P Mrinmay Sarkar
2024-02-28 14:02     ` Krzysztof Kozlowski

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