From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 586202900BA; Mon, 30 Jun 2025 17:17:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751303826; cv=none; b=upU0zfj+diI8gnzkFmMQV0oKssaI62hKlPfIXXxH9NpK8JlbZkusp1aW+6v1hphFVjrSUFqWDahI945CBye8iFP+/OSh7TsE6fSeh2RxgxAe12zuXQHb/fgtjzSgo7r7b4tURNRJE9QODGIiL/ZZ0Of7rsZzyHHIsrJ4bZtf89E= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751303826; c=relaxed/simple; bh=RxENiAIxryG/e9PnDRmuJ2qoeNevxHN+jSL1+CqMpqw=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=fHDN7ifSfRRY6Brj/5st0MCjspk5TK8OKf6ScFYYxaS/iMb7IoUrLblkKfCXEVPXHblIZwiCUT5ZwuH110+sHhpzuZyU/VjSv9dtNaZ4MqZ3SK+6BjPvYjvXp7pUZ3ckJiKKfnvZC/kqp1sCPA+DmsgvQdgTpTQ9zgMQbJC1PDM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gK7PLjxP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gK7PLjxP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DE5D1C4CEE3; Mon, 30 Jun 2025 17:17:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751303825; bh=RxENiAIxryG/e9PnDRmuJ2qoeNevxHN+jSL1+CqMpqw=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=gK7PLjxPWHRqv8leFMCxzAZgWK02KxZqRotqN8kQWL4Io69FgUlJ0Fo2ZgCYWBJlY CeCre45jA8BT+VMmEktD6EtSMdfkCjYyWxky07IUb4TgRoihvNGYCfGgHwN/OYSeif 9W7RDwjwepqgEJxMt/owvKqHaszwHtqfAaYrVyn+HOQrPRB1YiVjl2As0HL0IQExd1 Jv7zwgafCJbW98b7kjfQCCT4wE/cjPlopOmSyPb1pDVQLsBcTB0Kaekf+LAHdHsgfa vT0o7Yat4+natNFdPbKo49LdEHjQFKvQK+qt0Mx+usj4BSXqBwbItRTTQvMvp2YPRG Qh4Clax4BIHiA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uWI7r-00BJye-1d; Mon, 30 Jun 2025 18:17:03 +0100 Date: Mon, 30 Jun 2025 18:17:02 +0100 Message-ID: <86jz4tb14h.wl-maz@kernel.org> From: Marc Zyngier To: Lorenzo Pieralisi Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Arnd Bergmann , Sascha Bischoff , Jonathan Cameron , Timothy Hayes , Bjorn Helgaas , "Liam R. Howlett" , Peter Maydell , Mark Rutland , Jiri Slaby , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v6 00/31] Arm GICv5: Host driver implementation In-Reply-To: <20250626-gicv5-host-v6-0-48e046af4642@kernel.org> References: <20250626-gicv5-host-v6-0-48e046af4642@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: lpieralisi@kernel.org, tglx@linutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, sascha.bischoff@arm.com, Jonathan.Cameron@huawei.com, timothy.hayes@arm.com, bhelgaas@google.com, Liam.Howlett@oracle.com, peter.maydell@linaro.org, mark.rutland@arm.com, jirislaby@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 26 Jun 2025 11:25:51 +0100, Lorenzo Pieralisi wrote: > > Implement the irqchip kernel driver for the Arm GICv5 architecture, > as described in the GICv5 beta0 specification, available at: > > https://developer.arm.com/documentation/aes0070 > > The GICv5 architecture is composed of multiple components: > > - one or more IRS (Interrupt Routing Service) > - zero or more ITS (Interrupt Translation Service) > - zero or more IWB (Interrupt Wire Bridge) [...] I think what is here is pretty solid, and definitely in a better shape than the equivalent GICv3 support patches at a similar point in the lifetime of the architecture. For patches in this series except patch 18: Reviewed-by: Marc Zyngier If this goes into 6.17 (which I hope), it'd be good to have this series on a stable branch so that we can take the corresponding KVM patches[1] independently if they are deemed in a good enough state. M. [1] https://lore.kernel.org/r/20250627100847.1022515-1-sascha.bischoff@arm.com -- Without deviation from the norm, progress is not possible.