From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB8862DE6F1; Tue, 8 Jul 2025 14:41:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751985665; cv=none; b=J6GcFgE1bDsvjXp1KENuAlbN0IYMFbgpReP4mBtlUtGVKuYX4KqSQjDtdGpgXRWmqat6bJjVTdXzYsgyWtovPPGpHhxuj2hnrqqcCnTvxMrcOl1gUxYXOSdipIY9O834EKBUS8cEAFtLaj9D1g9GcuLSTN2V61iPr+5AzgkzONY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751985665; c=relaxed/simple; bh=o+9yZP3hCqGsyFTdJeQZPiXoMBkX1jh2XVuQmFEjmBI=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=nUpj7byENKVfemiKPluBByUBTJRMt+tTU+hOdfojTNPwqmZQ/X/RS392reQ+o/sz4pmHRaineGeVMWL8cjQiWduXNARkXVlRJOxapUjLLJE5uvERRLYf/T8NihvBLwxq66Xssu5YrBA1WeOrbDBks1ZjJzW0oUHn84HwTvDhugo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HA6JFNMO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HA6JFNMO" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6F1B7C4CEED; Tue, 8 Jul 2025 14:41:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751985664; bh=o+9yZP3hCqGsyFTdJeQZPiXoMBkX1jh2XVuQmFEjmBI=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=HA6JFNMOMFSvn2pwCigUy0Hy8cnFK32vInmMDrgIIzlhCd4zadfHcN6+Jcm7X/kvw 8S+sBSDS8BV3X1rOegvUktfHECu8ZK1skJMC/+4rblRv1M1pABfs/uPAnF2h5RtcT5 j/79hXxWJjvioOtJkwD2voNruTz9xO94Ta15VpxCylYQZsLwyWBwSrUrNoqVh01u5H 2FWo51N4iUt08dHwHSLkR/p0T1YVaHL1VrpfGtGjprJYphd/6nnZ0mrfRKYBK/NX5c JRq2PUOPuhZqplXmik4V372bk5ioHztN3OuQxOomD/ku3/HBX0nSu4UWznA9p+i5qN E7+lTqimx1UyA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uZ9VG-00DnGo-3G; Tue, 08 Jul 2025 15:41:02 +0100 Date: Tue, 08 Jul 2025 15:41:01 +0100 Message-ID: <86qzyqagoy.wl-maz@kernel.org> From: Marc Zyngier To: Lorenzo Pieralisi Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Toan Le , Krzysztof =?UTF-8?B?V2lsY3p5xYRza2k=?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Thomas Gleixner Subject: Re: [PATCH 09/12] PCI: xgene-msi: Sanitise MSI allocation and affinity setting In-Reply-To: References: <20250628173005.445013-1-maz@kernel.org> <20250628173005.445013-10-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: lpieralisi@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, toan@os.amperecomputing.com, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, tglx@linutronix.de X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 07 Jul 2025 15:57:47 +0100, Lorenzo Pieralisi wrote: > > On Sat, Jun 28, 2025 at 06:30:02PM +0100, Marc Zyngier wrote: [...] > > + * Effectively, this amounts to: > > + * - hwirq[7]::cpu[2:0] is the target frame number > > + * - hwirq[6:4] is the register index in any given frame > > + * - hwirq[3:0] is the MSI data > > I think that adding macros to define these subfields shifts would simplify > reading and reviewing the code - while reviewing xgene_msi_isr() I > realized it is hard to understand where the shifts to pack/unpack hwirq come > from. I'd understand you don't want to use FIELD_PREP/GET on hwirq, it > is not a HW field but rather a SW encoding you created but at least defining > the shifts and using them throughout would help. I have no problem using FIELD_*() for that. I've now reworked this to make it clearer as well as added a bit more documentation on the behaviour of the MSInRx registers (they are quite funky). Thanks, M. -- Without deviation from the norm, progress is not possible.