From: Nathan Lynch <nathan.lynch@amd.com>
To: Karim Manaouil <kmanaouil.dev@gmail.com>
Cc: <shivankg@amd.com>, <Stephen.Bates@amd.com>,
<PradeepVineshReddy.Kodamati@amd.com>,
<dmaengine@vger.kernel.org>, <linux-pci@vger.kernel.org>
Subject: Re: SDXI on AMD EPYC (in relation to Nathan’s SDXI dmaengine patchset)
Date: Tue, 23 Jun 2026 08:10:04 -0500 [thread overview]
Message-ID: <875x39ies3.fsf@amd.com> (raw)
In-Reply-To: <20260623103204.qvmd5luse4vmhwl3@wrangler>
Karim Manaouil <kmanaouil.dev@gmail.com> writes:
>
> I have a dual-socket AMD EPYC 9004 in the lab (I pasted /proc/cpuinfo at
> the end) and I wanted to see if I can get the SDXI series from Nathan [2]
> to work on them, as this will open the door for me to experiment more on
> AMD hardware.
>
> I don't know if these CPUs are equipped with these accelerators or not.
> lspci is showing these devices (four on each NUMA node):
>
> # lspci | grep SDXI
> 06:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> 21:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> 41:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> 64:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> 81:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> a3:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> c1:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> e1:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
>
> All of them have these PCI specs
>
> vendor=0x1022
> device=0x14dc
> class=0x088000
> subsystem_vendor=0x1458
> subsystem_device=0x1000
> BARs= BAR0/1 512 KiB prefetchable
> BAR2/3 512 KiB prefetchable
>
> Class 0x088000 is:
> base class 0x08 System peripheral
> subclass 0x80 Other system peripheral
>
> However, the PCI device class does not actually match the class from
> Nathan's patchset [2]:
>
> +#define PCI_CLASS_ACCELERATOR_SDXI 0x120100
>
> +static const struct pci_device_id sdxi_id_table[] = {
> + { PCI_DEVICE_CLASS(PCI_CLASS_ACCELERATOR_SDXI, 0xffffff) },
> + { }
> +};
>
> So these functions appear to be exposed as generic system peripherals
> (base class 0x08, subclass 0x80) rather than as SDXI processing
> accelerators (base class 0x12, subclass 0x01).
>
> Do you know whether these AMD 1022:14dc on this platform are actually
> SDXI accelerators?
Afraid I don't have any information about these devices. The driver
isn't intended to support them.
next prev parent reply other threads:[~2026-06-23 13:10 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-23 10:32 SDXI on AMD EPYC (in relation to Nathan’s SDXI dmaengine patchset) Karim Manaouil
2026-06-23 13:10 ` Nathan Lynch [this message]
2026-06-23 14:32 ` Karim Manaouil
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=875x39ies3.fsf@amd.com \
--to=nathan.lynch@amd.com \
--cc=PradeepVineshReddy.Kodamati@amd.com \
--cc=Stephen.Bates@amd.com \
--cc=dmaengine@vger.kernel.org \
--cc=kmanaouil.dev@gmail.com \
--cc=linux-pci@vger.kernel.org \
--cc=shivankg@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox