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Wed, 07 Jan 2026 05:45:45 -0800 (PST) Received: from razdolb ([77.220.204.220]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-59b669418b6sm1224545e87.20.2026.01.07.05.45.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Jan 2026 05:45:45 -0800 (PST) References: <20251216-upstream_pcie_rc-v7-0-4aeb0f53c4ce@aspeedtech.com> <875x9fuj7i.fsf@gmail.com> User-agent: mu4e 1.10.9; emacs 30.2 From: Mikhail Rudenko To: Jacky Chou Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Linus Walleij , Philipp Zabel , Neil Armstrong , "linux-aspeed@lists.ozlabs.org" , "linux-pci@vger.kernel.org" , "linux-phy@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Andrew Jeffery , "openbmc@lists.ozlabs.org" , "linux-gpio@vger.kernel.org" Subject: Re: [PATCH v7 0/7] Add ASPEED PCIe Root Complex support Date: Wed, 07 Jan 2026 16:40:09 +0300 In-reply-to: Message-ID: <875x9dcz9c.fsf@gmail.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain Hi Jacky, On 2026-01-07 at 02:28 GMT, Jacky Chou wrote: > Hi Mikhail Rudenko, > >> First of all, thank you for your efforts in getting this driver upstreamed! I am >> trying to understand whether this driver supports PCIe devices that have an I/O >> port BAR, where CPU access to I/O ports is required for proper device >> operation. >> >> If I understand correctly, this line in the Aspeed 2600 dtsi file declares the I/O >> port range: >> >> ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000 >> >> During system initialization, the pci_remap_iospace() function in >> arch/arm/mm/ioremap.c maps the physical address range >> 0x00018000-0x00020000 to the virtual address PCI_IO_VIRT_BASE >> (0xfee00000). After this mapping, inb() and outb() calls work by converting I/O >> port addresses to virtual addresses starting at PCI_IO_VIRT_BASE, then >> performing reads and writes to those virtual addresses. >> >> What I don't understand is this: according to the Aspeed 2600 datasheet, the >> address range 0x00000000-0x0fffffff (which contains >> 0x00018000-0x00020000) is mapped to Firmware SPI Memory. This would >> mean that outb() operations get routed to memory-mapped SPI flash instead of >> PCIe. >> >> It seems like there's a missing piece to this puzzle. Could you help clarify how >> this is supposed to work? >> > > Thank you for pointing this out, and sorry for the confusion. > > You are correct that, as things stand, this does not make sense from a real hardware perspective. > > In fact, the I/O addressing support you noticed was something we experimented with internally > only. There is no actual hardware design on AST2600 that supports PCIe I/O port addressing in > this way. To enable those experiments, we modified our internal kernel accordingly, but this was > never intended to represent real, supported hardware behavior. > > This is our mistake for leaving this description in the DTS, as it can indeed be misleading. We > will remove this part to avoid further confusion. > > Thank you again for your careful review and for bringing this to our attention. Thank you for prompt reply and for getting this clarified! > Thanks, > Jacky -- Kind regards, Mikhail