[PATCH v7 5/7] PCI: Add FMT, TYPE and CPL status definition for TLP header

Jacky Chou
2025-12-16T01:50:21Z

According to PCIe specification, add FMT, TYPE and CPL status
definition for TLP header.

Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
---
drivers/pci/pci.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)

diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 0e67014aa001..81f2e633b116 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -63,6 +63,18 @@ struct pcie_tlp_log;
#define PCIE_LINK_WAIT_MAX_RETRIES 10
#define PCIE_LINK_WAIT_SLEEP_MS 90

+/* Format of TLP; PCIe r7.0, sec 2.2.1 */
+#define PCIE_TLP_FMT_3DW_NO_DATA 0x00 /* 3DW header, no data */
+#define PCIE_TLP_FMT_4DW_NO_DATA 0x01 /* 4DW header, no data */
+#define PCIE_TLP_FMT_3DW_DATA 0x02 /* 3DW header, with data */
+#define PCIE_TLP_FMT_4DW_DATA 0x03 /* 4DW header, with data */
+
+/* Type of TLP; PCIe r7.0, sec 2.2.1 */
+#define PCIE_TLP_TYPE_CFG0_RD 0x04 /* Config Type 0 Read Request */
+#define PCIE_TLP_TYPE_CFG0_WR 0x04 /* Config Type 0 Write Request */
+#define PCIE_TLP_TYPE_CFG1_RD 0x05 /* Config Type 1 Read Request */
+#define PCIE_TLP_TYPE_CFG1_WR 0x05 /* Config Type 1 Write Request */
+
/* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */
#define PCIE_MSG_TYPE_R_RC 0
#define PCIE_MSG_TYPE_R_ADDR 1
@@ -84,6 +96,9 @@ struct pcie_tlp_log;
#define PCIE_MSG_CODE_DEASSERT_INTC 0x26
#define PCIE_MSG_CODE_DEASSERT_INTD 0x27

+/* Cpl. status of Complete; PCIe r7.0, sec 2.2.9.1 */
+#define PCIE_CPL_STS_SUCCESS 0x00 /* Successful Completion */
+
#define PCI_BUS_BRIDGE_IO_WINDOW 0
#define PCI_BUS_BRIDGE_MEM_WINDOW 1
#define PCI_BUS_BRIDGE_PREF_MEM_WINDOW 2

--
2.34.1