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Tue, 06 Jan 2026 02:30:32 -0800 (PST) Received: from razdolb ([77.220.204.220]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-382eb8dadc0sm4315921fa.33.2026.01.06.02.30.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jan 2026 02:30:32 -0800 (PST) References: <20251216-upstream_pcie_rc-v7-0-4aeb0f53c4ce@aspeedtech.com> User-agent: mu4e 1.10.9; emacs 30.2 From: Mikhail Rudenko To: Jacky Chou Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Linus Walleij , Philipp Zabel , Neil Armstrong , linux-aspeed@lists.ozlabs.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andrew Jeffery , openbmc@lists.ozlabs.org, linux-gpio@vger.kernel.org, Mikhail Rudenko Subject: Re: [PATCH v7 0/7] Add ASPEED PCIe Root Complex support Date: Tue, 06 Jan 2026 12:58:40 +0300 In-reply-to: <20251216-upstream_pcie_rc-v7-0-4aeb0f53c4ce@aspeedtech.com> Message-ID: <875x9fuj7i.fsf@gmail.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain Hi Jacky, On 2025-12-16 at 09:49 +08, Jacky Chou wrote: > This patch series adds support for the ASPEED PCIe Root Complex, > including device tree bindings, pinctrl support, and the PCIe host controller > driver. The patches introduce the necessary device tree nodes, pinmux groups, > and driver implementation to enable PCIe functionality on ASPEED platforms. > Currently, the ASPEED PCIe Root Complex only supports a single port. > > Summary of changes: > - Add device tree binding documents for ASPEED PCIe PHY and PCIe RC > - Update MAINTAINERS for new bindings and driver > - Implement ASPEED PCIe PHY driver > - Implement ASPEED PCIe Root Complex host controller driver > > This series has been tested on AST2600/AST2700 platforms and enables PCIe device > enumeration and operation. First of all, thank you for your efforts in getting this driver upstreamed! I am trying to understand whether this driver supports PCIe devices that have an I/O port BAR, where CPU access to I/O ports is required for proper device operation. If I understand correctly, this line in the Aspeed 2600 dtsi file declares the I/O port range: ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000 During system initialization, the pci_remap_iospace() function in arch/arm/mm/ioremap.c maps the physical address range 0x00018000-0x00020000 to the virtual address PCI_IO_VIRT_BASE (0xfee00000). After this mapping, inb() and outb() calls work by converting I/O port addresses to virtual addresses starting at PCI_IO_VIRT_BASE, then performing reads and writes to those virtual addresses. What I don't understand is this: according to the Aspeed 2600 datasheet, the address range 0x00000000-0x0fffffff (which contains 0x00018000-0x00020000) is mapped to Firmware SPI Memory. This would mean that outb() operations get routed to memory-mapped SPI flash instead of PCIe. It seems like there's a missing piece to this puzzle. Could you help clarify how this is supposed to work? -- Kind regards, Mikhail Rudenko