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X-CSE-ConnectionGUID: XS4cYT96TMGkCtwW6hdnOw== X-CSE-MsgGUID: YYbvfmZgRFevto/RVzUQJg== X-IronPort-AV: E=McAfee;i="6700,10204,11129"; a="17889868" X-IronPort-AV: E=Sophos;i="6.09,198,1716274800"; d="scan'208";a="17889868" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2024 07:21:05 -0700 X-CSE-ConnectionGUID: VfoH+6bHS6yJvt/tx0S6yg== X-CSE-MsgGUID: PiRkMKV8R/iT/dFMPm8JHQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,198,1716274800"; d="scan'208";a="85737647" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.125]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2024 07:21:02 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Wed, 10 Jul 2024 17:20:58 +0300 (EEST) To: George-Daniel Matei cc: Bjorn Helgaas , LKML , linux-pci@vger.kernel.org Subject: Re: [PATCH] PCI: r8169: add suspend/resume aspm quirk In-Reply-To: <20240708153815.2757367-1-danielgeorgem@chromium.org> Message-ID: <87b22115-2b88-db66-f97c-aa8eea22f8cf@linux.intel.com> References: <20240708153815.2757367-1-danielgeorgem@chromium.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII On Mon, 8 Jul 2024, George-Daniel Matei wrote: > Added aspm suspend/resume hooks that run > before and after suspend and resume to change > the ASPM states of the PCI bus in order to allow > the system suspend while trying to prevent card hangs > > Signed-off-by: George-Daniel Matei > --- > drivers/pci/quirks.c | 142 +++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 142 insertions(+) > > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c > index dc12d4a06e21..aa3dba2211d3 100644 > --- a/drivers/pci/quirks.c > +++ b/drivers/pci/quirks.c > @@ -6189,6 +6189,148 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency > DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency); > DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency); > DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency); > + > +static const struct dmi_system_id chromebox_match_table[] = { > + { > + .matches = { > + DMI_MATCH(DMI_PRODUCT_NAME, "Brask"), > + DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"), > + } > + }, > + { > + .matches = { > + DMI_MATCH(DMI_PRODUCT_NAME, "Aurash"), > + DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"), > + } > + }, > + { > + .matches = { > + DMI_MATCH(DMI_PRODUCT_NAME, "Bujia"), > + DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"), > + } > + }, > + { > + .matches = { > + DMI_MATCH(DMI_PRODUCT_NAME, "Gaelin"), > + DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"), > + } > + }, > + { > + .matches = { > + DMI_MATCH(DMI_PRODUCT_NAME, "Gladios"), > + DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"), > + } > + }, > + { > + .matches = { > + DMI_MATCH(DMI_PRODUCT_NAME, "Hahn"), > + DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"), > + } > + }, > + { > + .matches = { > + DMI_MATCH(DMI_PRODUCT_NAME, "Jeev"), > + DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"), > + } > + }, > + { > + .matches = { > + DMI_MATCH(DMI_PRODUCT_NAME, "Kinox"), > + DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"), > + } > + }, > + { > + .matches = { > + DMI_MATCH(DMI_PRODUCT_NAME, "Kuldax"), > + DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"), > + } > + }, > + { > + .matches = { > + DMI_MATCH(DMI_PRODUCT_NAME, "Lisbon"), > + DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"), > + } > + }, > + { > + .matches = { > + DMI_MATCH(DMI_PRODUCT_NAME, "Moli"), > + DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"), > + } > + }, > + { } > +}; > + > +static void rtl8169_suspend_aspm_settings(struct pci_dev *dev) > +{ > + u16 val = 0; > + > + if (dmi_check_system(chromebox_match_table)) { > + //configure parent Missing space. > + pcie_capability_clear_and_set_word(dev->bus->self, > + PCI_EXP_LNKCTL, > + PCI_EXP_LNKCTL_ASPMC, > + PCI_EXP_LNKCTL_ASPM_L1); > + > + pci_read_config_word(dev->bus->self, > + dev->bus->self->l1ss + PCI_L1SS_CTL1, > + &val); > + val = (val & ~PCI_L1SS_CTL1_L1SS_MASK) | > + PCI_L1SS_CTL1_PCIPM_L1_2 | PCI_L1SS_CTL1_PCIPM_L1_2 | > + PCI_L1SS_CTL1_ASPM_L1_1; > + pci_write_config_word(dev->bus->self, > + dev->bus->self->l1ss + PCI_L1SS_CTL1, > + val); Touching ASPM state should be done through aspm driver, not by writing directly into LNKCTL and L1SS registers. > + //configure device Missing space. > + pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL, > + PCI_EXP_LNKCTL_ASPMC, > + PCI_EXP_LNKCTL_ASPM_L1); > + > + pci_read_config_word(dev, dev->l1ss + PCI_L1SS_CTL1, &val); > + val = (val & ~PCI_L1SS_CTL1_L1SS_MASK) | > + PCI_L1SS_CTL1_PCIPM_L1_2 | PCI_L1SS_CTL1_PCIPM_L1_2 | > + PCI_L1SS_CTL1_ASPM_L1_1; > + pci_write_config_word(dev, dev->l1ss + PCI_L1SS_CTL1, val); > + } > +} > + > +DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_REALTEK, 0x8168, > + rtl8169_suspend_aspm_settings); > + > +static void rtl8169_resume_aspm_settings(struct pci_dev *dev) > +{ > + u16 val = 0; > + > + if (dmi_check_system(chromebox_match_table)) { > + //configure device Missing space > + pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL, > + PCI_EXP_LNKCTL_ASPMC, 0); pcie_capability_clear_word() > + > + pci_read_config_word(dev->bus->self, A copy-paste error for the device??? > + dev->bus->self->l1ss + PCI_L1SS_CTL1, > + &val); > + val = val & ~PCI_L1SS_CTL1_L1SS_MASK; > + pci_write_config_word(dev->bus->self, > + dev->bus->self->l1ss + PCI_L1SS_CTL1, > + val); > + > + //configure parent Missing space > + pcie_capability_clear_and_set_word(dev->bus->self, > + PCI_EXP_LNKCTL, > + PCI_EXP_LNKCTL_ASPMC, 0); pcie_capability_clear_and_set_word() > + > + pci_read_config_word(dev->bus->self, > + dev->bus->self->l1ss + PCI_L1SS_CTL1, > + &val); > + val = val & ~PCI_L1SS_CTL1_L1SS_MASK; > + pci_write_config_word(dev->bus->self, > + dev->bus->self->l1ss + PCI_L1SS_CTL1, > + val); Touching the same device twice here? > + } > +} > + > +DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_REALTEK, 0x8168, > + rtl8169_resume_aspm_settings); > #endif -- i.