From: Thomas Gleixner <tglx@linutronix.de>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: LKML <linux-kernel@vger.kernel.org>,
x86@kernel.org, Joerg Roedel <joro@8bytes.org>,
Will Deacon <will@kernel.org>,
linux-pci@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Marc Zyngier <maz@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Dave Jiang <dave.jiang@intel.com>,
Alex Williamson <alex.williamson@redhat.com>,
Kevin Tian <kevin.tian@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Logan Gunthorpe <logang@deltatee.com>,
Ashok Raj <ashok.raj@intel.com>, Jon Mason <jdmason@kudzu.us>,
Allen Hubbe <allenbh@gmail.com>,
"Ahmed S. Darwish" <darwi@linutronix.de>,
Reinette Chatre <reinette.chatre@intel.com>
Subject: Re: [patch 21/33] genirq/msi: Provide msi_domain_alloc_irq_at()
Date: Thu, 17 Nov 2022 10:40:50 +0100 [thread overview]
Message-ID: <87r0y1nckd.ffs@tglx> (raw)
In-Reply-To: <Y3U7oeW7jfEDv0Qu@nvidia.com>
On Wed, Nov 16 2022 at 15:36, Jason Gunthorpe wrote:
> On Fri, Nov 11, 2022 at 02:58:44PM +0100, Thomas Gleixner wrote:
>> The function also takes an optional @cookie argument which is of type union
>> msi_dev_cookie. This cookie is not used by the core code and is stored in
>> the allocated msi_desc::data::cookie. The meaning of the cookie is
>> completely implementation defined. In case of IMS this might be a PASID or
>> a pointer to a device queue, but for the MSI core it's opaque and not used
>> in any way.
>
> To my mind it makes more sense to pass a 'void *' through from
> msi_domain_alloc_irq_at() to the prepare_desc() op with the idea that
> the driver calling msi_domain_alloc_irq_at() knows it is calling it
> against the domain that it allocated. The prepare_desc can then use
> the void * to properly initialize anything about the desc under the
> right lock.
You are looking at it from one particular use case.
> Before calling this the driver should have setup whatever thing is
> going to originate the interrupt, eg allocated the HW object that
> sources the interrupt and part of what the void * would convey is the
> detailed information on how to program the HW object. eg IDXD is using
> an iobase and an offset along with the enforcing PASID, but something
> like mlx5 would probably want an object id, type, and SF ID.
Correct, and that's why the cookie is there. You can stash your pointer
into the cookie and an IDXD user stores the PASID. The IDXD user which
allocates an interrupt does not even know about iobase and offset. It
does neither care about what the IDXD irq domain implementation does
with that cookie.
Neither should your queue code care. The queue driver code puts a
pointer to struct mlx5_voodoo into the cookie when allocating the
interrupt and then the mlx5 irqdomain code which is a complete separate
entity gets this cookie handed into prepare_desc().
struct mlx5_voodoo contains all information for the irq domain code to
set up the necessary things in the queue. That must be obviously a
contract between the queue code and the irqdomain code but that's not
any different than MSI or MSI-X. The only difference is that in the IMS
case the contract is per device and not codified in a standard.
> This is again where I don't much like the use of an ID to refer to the
> domain.
>
> Having the driver allocate the device domain, retain a pointer to it,
> and use that domain pointer with all these new APIs seems much clearer
> than converting the pointer to an ID.
You're really obsessed about this irqdomain pointer, right?
You have to differentiate between the irq domain implementation and the
actual usage sites and not conflate them into one thing.
Let's look at the usage site:
struct cookie cookie = { .ptr = mymagicqueue, }
pci_ims_alloc_irq(pci_dev, &cookie);
versus:
struct cookie cookie = { .ptr = mymagicqueue, }
ims_alloc_irq(&pci_dev->dev, mydev->ims_domain, &cookie);
Even in the unlikely case that we have more than two domains, then still
the usage site has zero interest in the domain pointer:
struct cookie cookie = { .ptr = mymagicqueue, }
pci_ims_alloc_irq(pci_dev, myqueue->domid, &cookie);
where the code which instantiates myqueue sets up domid.
The usage site has absolutely no business to touch irqdomain pointer or
to even know that one exists. All it needs to know is how the cookie
contract works, obviously.
Now the functions you need in your irqdomain implementation to
e.g. prepare the MSI descriptor surely need to know about the irqdomain
pointer, but that gets handed in from the allocation code so the prepare
function knows which instance it is operating on.
So what does the irqdomain pointer buy you? Exactly nothing!
Look at the IDXD reference implementation.
The IDXD probe code which initializes the physical device
instantiates the irq domain along with the iobase for the
storage array.
The actual queue (or whatever IDXD names it) setup code just sticks
PASID into the cookie and allocates an interrupt. It gets a virtual
irq number and requests the interrupt.
Where is the need for a pointer? The queue code does not even know about
the iobase of the storage array. It's completely irrelevant there. All
it has to know is the cookie contract, not more.
Let's take you pointer obsession to the extreme:
struct irq_desc *desc = pci_alloc_msix_interrupt(pci_dev);
request_irq(desc, handler, pci_dev);
versus:
int virq = pci_alloc_msix_interrupt(pci_dev);
request_irq(virq, handler, pci_dev);
You could argue the same way that there is no need for a Linux interrupt
number and we could just use the interrupt descriptor pointer.
Sure, you can do that, but then you violate _all_ encapsulation rules in
one go for absolutely _ZERO_ value.
Want another example based on kmalloc()?
Almost 20 years ago I did a treewide mopup of drivers which decided that
they need to fiddle in the irq descriptor for the very wrong reasons.
I had to do that to be able to do a trivial change in the core code...
C is patently bad for encapsulation, but you can make it worse by
forcefully ignoring the design patterns which allow to completely hide
implementation details of a subsystem or infrastructure.
If you look at the last commit in the ARM part of this work:
https://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git/commit/?h=devmsi-arm&id=96c97746cbb431a306e95c04d6b3c75751244716
then you can see the final move to remove the visibility of
the MSI management internals.
This makes it possible to completely overhaul the inner workings of the
MSI core without having to chase abuse all over the place.
Thanks,
tglx
next prev parent reply other threads:[~2022-11-17 9:40 UTC|newest]
Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-11 13:58 [patch 00/33] genirq, PCI/MSI: Support for per device MSI and PCI/IMS - Part 3 implementation Thomas Gleixner
2022-11-11 13:58 ` [patch 01/33] genirq/msi: Rearrange MSI domain flags Thomas Gleixner
2022-11-16 18:41 ` Jason Gunthorpe
2022-11-11 13:58 ` [patch 02/33] genirq/msi: Provide struct msi_parent_ops Thomas Gleixner
2022-11-16 18:57 ` Jason Gunthorpe
2022-11-17 15:58 ` Thomas Gleixner
2022-11-18 13:52 ` Thomas Gleixner
2022-11-11 13:58 ` [patch 03/33] genirq/msi: Provide data structs for per device domains Thomas Gleixner
2022-11-11 13:58 ` [patch 04/33] genirq/msi: Add size info to struct msi_domain_info Thomas Gleixner
2022-11-11 13:58 ` [patch 05/33] genirq/msi: Split msi_create_irq_domain() Thomas Gleixner
2022-11-11 13:58 ` [patch 06/33] genirq/irqdomain: Add irq_domain::dev for per device MSI domains Thomas Gleixner
2022-11-11 13:58 ` [patch 07/33] genirq/msi: Provide msi_create/free_device_irq_domain() Thomas Gleixner
2022-11-11 13:58 ` [patch 08/33] genirq/msi: Provide msi_match_device_domain() Thomas Gleixner
2022-11-11 13:58 ` [patch 09/33] genirq/msi: Add range checking to msi_insert_desc() Thomas Gleixner
2022-11-11 13:58 ` [patch 10/33] PCI/MSI: Split __pci_write_msi_msg() Thomas Gleixner
2022-11-16 20:10 ` Bjorn Helgaas
2022-11-11 13:58 ` [patch 11/33] genirq/msi: Provide BUS_DEVICE_PCI_MSI[X] Thomas Gleixner
2022-11-11 13:58 ` [patch 12/33] PCI/MSI: Add support for per device MSI[X] domains Thomas Gleixner
2022-11-16 19:13 ` Jason Gunthorpe
2022-11-16 22:38 ` Thomas Gleixner
2022-11-17 0:22 ` Jason Gunthorpe
2022-11-17 8:45 ` Thomas Gleixner
2022-11-16 20:22 ` Bjorn Helgaas
2022-11-11 13:58 ` [patch 13/33] x86/apic/vector: Provide MSI parent domain Thomas Gleixner
2022-11-16 19:18 ` Jason Gunthorpe
2022-11-17 20:06 ` Thomas Gleixner
2022-11-11 13:58 ` [patch 14/33] PCI/MSI: Remove unused pci_dev_has_special_msi_domain() Thomas Gleixner
2022-11-16 20:13 ` Bjorn Helgaas
2022-11-11 13:58 ` [patch 15/33] iommu/vt-d: Switch to MSI parent domains Thomas Gleixner
2022-11-11 13:58 ` [patch 16/33] iommu/amd: Switch to MSI base domains Thomas Gleixner
2022-11-11 13:58 ` [patch 17/33] x86/apic/msi: Remove arch_create_remap_msi_irq_domain() Thomas Gleixner
2022-11-11 13:58 ` [patch 18/33] genirq/msi: Provide struct msi_map Thomas Gleixner
2022-11-11 13:58 ` [patch 19/33] genirq/msi: Provide msi_desc::msi_data Thomas Gleixner
2022-11-16 19:28 ` Jason Gunthorpe
2022-11-17 8:48 ` Thomas Gleixner
2022-11-17 13:33 ` Jason Gunthorpe
2022-11-18 22:08 ` Thomas Gleixner
2022-11-21 17:20 ` Jason Gunthorpe
2022-11-21 19:40 ` Thomas Gleixner
2022-11-22 1:52 ` Jason Gunthorpe
2022-11-22 20:49 ` Thomas Gleixner
2022-11-23 16:58 ` Jason Gunthorpe
2022-11-23 18:38 ` Thomas Gleixner
2022-12-01 12:24 ` Thomas Gleixner
2022-12-02 0:35 ` Jason Gunthorpe
2022-12-02 2:14 ` Thomas Gleixner
2022-11-11 13:58 ` [patch 20/33] genirq/msi: Provide msi_domain_ops::prepare_desc() Thomas Gleixner
2022-11-11 13:58 ` [patch 21/33] genirq/msi: Provide msi_domain_alloc_irq_at() Thomas Gleixner
2022-11-16 19:36 ` Jason Gunthorpe
2022-11-17 9:40 ` Thomas Gleixner [this message]
2022-11-17 23:33 ` Reinette Chatre
2022-11-18 0:58 ` Thomas Gleixner
2022-11-18 9:15 ` Thomas Gleixner
2022-11-18 11:05 ` Thomas Gleixner
2022-11-18 18:18 ` Reinette Chatre
2022-11-18 22:31 ` Thomas Gleixner
2022-11-18 22:59 ` Reinette Chatre
2022-11-19 0:19 ` Reinette Chatre
2022-11-11 13:58 ` [patch 22/33] genirq/msi: Provide MSI_FLAG_MSIX_ALLOC_DYN Thomas Gleixner
2022-11-16 19:36 ` Jason Gunthorpe
2022-11-11 13:58 ` [patch 23/33] PCI/MSI: Split MSIX descriptor setup Thomas Gleixner
2022-11-16 20:13 ` Bjorn Helgaas
2022-11-11 13:58 ` [patch 24/33] PCI/MSI: Provide prepare_desc() MSI domain op Thomas Gleixner
2022-11-16 19:40 ` Jason Gunthorpe
2022-11-16 20:26 ` Bjorn Helgaas
2022-11-16 22:42 ` Thomas Gleixner
2022-11-11 13:58 ` [patch 25/33] PCI/MSI: Provide post-enable dynamic allocation interfaces for MSI-X Thomas Gleixner
2022-11-16 20:19 ` Bjorn Helgaas
2022-11-16 22:43 ` Thomas Gleixner
2022-11-11 13:58 ` [patch 26/33] x86/apic/msi: Enable MSI_FLAG_PCI_MSIX_ALLOC_DYN Thomas Gleixner
2022-11-11 13:58 ` [patch 27/33] genirq/msi: Provide constants for PCI/IMS support Thomas Gleixner
2022-11-16 19:54 ` Jason Gunthorpe
2022-11-17 9:46 ` Thomas Gleixner
2022-11-11 13:58 ` [patch 28/33] PCI/MSI: Provide IMS (Interrupt Message Store) support Thomas Gleixner
2022-11-16 20:17 ` Bjorn Helgaas
2022-11-11 13:58 ` [patch 29/33] PCI/MSI: Provide pci_ims_alloc/free_irq() Thomas Gleixner
2022-11-16 20:14 ` Bjorn Helgaas
2022-11-11 13:58 ` [patch 30/33] x86/apic/msi: Enable PCI/IMS Thomas Gleixner
2022-11-11 13:59 ` [patch 31/33] iommu/vt-d: " Thomas Gleixner
2022-11-11 13:59 ` [patch 32/33] iommu/amd: " Thomas Gleixner
2022-11-11 13:59 ` [patch 33/33] irqchip: Add IDXD Interrupt Message Store driver Thomas Gleixner
2022-12-02 17:55 ` Reinette Chatre
2022-12-02 19:51 ` Thomas Gleixner
2022-12-02 21:16 ` Reinette Chatre
2022-12-05 15:20 ` Thomas Gleixner
2022-12-05 17:19 ` Reinette Chatre
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87r0y1nckd.ffs@tglx \
--to=tglx@linutronix.de \
--cc=alex.williamson@redhat.com \
--cc=allenbh@gmail.com \
--cc=ashok.raj@intel.com \
--cc=bhelgaas@google.com \
--cc=dan.j.williams@intel.com \
--cc=darwi@linutronix.de \
--cc=dave.jiang@intel.com \
--cc=gregkh@linuxfoundation.org \
--cc=jdmason@kudzu.us \
--cc=jgg@nvidia.com \
--cc=joro@8bytes.org \
--cc=kevin.tian@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=logang@deltatee.com \
--cc=lorenzo.pieralisi@arm.com \
--cc=maz@kernel.org \
--cc=reinette.chatre@intel.com \
--cc=will@kernel.org \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).