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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6760fbb2esm985639866b.140.2025.01.29.05.54.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 29 Jan 2025 05:54:42 -0800 (PST) Message-ID: <8acfd9b2-caae-4fe7-8d37-19e2d9be23a8@suse.com> Date: Wed, 29 Jan 2025 14:54:41 +0100 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: Config space access to Mediatek MT7922 doesn't work after device reset in Xen PV dom0 (regression, Linux 6.12) To: Bjorn Helgaas Cc: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , Bjorn Helgaas , =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Boris Ostrovsky , xen-devel , linux-kernel@vger.kernel.org, regressions@lists.linux.dev, Felix Fietkau , Lorenzo Bianconi , Ryder Lee , linux-pci@vger.kernel.org References: <20250129132843.GA451331@bhelgaas> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250129132843.GA451331@bhelgaas> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 29.01.2025 14:28, Bjorn Helgaas wrote: > On Wed, Jan 29, 2025 at 10:17:20AM +0100, Jan Beulich wrote: >> On 29.01.2025 04:22, Marek Marczykowski-Górecki wrote: >>> On Tue, Jan 28, 2025 at 09:03:15PM -0600, Bjorn Helgaas wrote: >>>> The report claims the problem only happens with Xen. I'm not a Xen >>>> person, and I don't know how to find the relevant config accessors. >>>> The snippets of kernel messages I see at [1] all mention pciback, so >>>> that's my only clue of where to look. Bottom line, I have no idea >>>> what the config accessor path is, and maybe we could learn something >>>> by looking at whatever it is. >>> >>> AFAIK there are no separate config accessors under Xen dom0, the default >>> ones are used. xen-pcifront takes over PCI config space access (and few >>> more) only in a domU (and only for PV), when PCI passthrough is used. >>> Here, it didn't went that far... >>> >>> But then, Xen may intercept such access [2]. If I read it right, it >>> should allow all access (is_hardware_domain(dom0)==true, and also the >>> device is not on ro_map - otherwise reset wouldn't work at all). >> >> The other day you mentioned (on Matrix I think) that you observe mmcfg >> not being used on that system. Am I misremembering? (Since the capability >> where the control bit lives is an extended one, that capability would >> neither be read nor modified when mmcfg is unavailable.) > > If you're referring to the Configuration RRS Software Visibility > Enable bit, that's in the PCIe Capability Root Control register, which > is in the PCI-compatible config space (the first 256 bytes), not the > extended config space. Oh, I clearly didn't read Marek's earlier mail correctly. I'm sorry for that. Jan