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Fri, 14 Aug 2026 09:55:25 -0700 (PDT) Message-ID: <8c33e30a-e35e-47d4-a851-c82e18ed7472@riscstar.com> Date: Fri, 14 Aug 2026 11:55:23 -0500 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] dt-bindings: misc: introduce pci1179,0220.yaml To: Krzysztof Kozlowski Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, bhelgaas@google.com, daniel@riscstar.com, mohdayaa@qti.qualcomm.com, lbiancon@qti.qualcomm.com, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260813222943.1655453-1-elder@riscstar.com> <20260813222943.1655453-2-elder@riscstar.com> <20260814-deft-unnatural-teal-1dbac3@quoll> Content-Language: en-US From: Alex Elder In-Reply-To: <20260814-deft-unnatural-teal-1dbac3@quoll> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 8/14/26 2:01 AM, Krzysztof Kozlowski wrote: > On Thu, Aug 13, 2026 at 05:29:41PM -0500, Alex Elder wrote: >> Define the binding for the Toshiba TC9564 PCI endpoint function device. >> The third downstream PCIe switch port within this chip has an embedded >> PCIe controller, and that implements two of these PCIe functions. >> >> Signed-off-by: Daniel Thompson >> Signed-off-by: Alex Elder >> --- >> .../bindings/misc/pci1179,0220.yaml | 150 ++++++++++++++++++ >> MAINTAINERS | 6 + >> 2 files changed, 156 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/misc/pci1179,0220.yaml >> > > There are no properties in the binding except standard PCIe ones, so why > do you need it in DT in the first place? We do not describe PCI devices > in DT by default, so you are doing something unusual. Commit msg should > explain that. Maybe because it's using pci-ep-bus? I'm not sure I can answer your question though. An earlier version used auxiliary devices. This time the PCI device sort of stands by itself as provider of the endpoint buses that are used by other devices within the SoC. There is otherwise no single driver (e.g., for an Ethernet interface) that is implemented as a PCI driver to bind with the hardware. The SoC drivers will all be platform drivers. If you don't think this is needed, I'll gladly accept that. But the PCI endpoint bus is a devicetree construct, and it seemed to me that using it needed to be documented somehow. I'd appreciate guidance on how to think about it so I can document it properly (or not). Thanks. -Alex > Best regards, > Krzysztof >