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[2001:1ae9:ff1:f191:401f:749d:725f:a2a7]) by smtp.gmail.com with ESMTPSA id r7-v6sm1617613wrt.0.2018.09.22.14.06.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 22 Sep 2018 14:06:08 -0700 (PDT) From: Petr Cvek Subject: mt7621/mt7628 PCIe linux driver To: ryder.lee@mediatek.com, blogic@openwrt.org, sergio.paracuellos@gmail.com Cc: linux-mediatek@lists.infradead.org, linux-mips@linux-mips.org, linux-pci@vger.kernel.org Message-ID: <8fd595af-53fa-c100-c369-8c7a30eba8e3@gmail.com> Date: Sat, 22 Sep 2018 23:06:50 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Hello, I'm trying to play with mt7628 PCIe (and it's old driver mt7620), but the system keeps freezing. It is probably because of bus master access of my PCIe cards but I don't see any memory access controls for PCIe <-> RAM in the datasheet. The same problem is with MSI. It seems the root complex supports MSI (it has an MSI capability field), but there isn't any mention in the MT7628 datasheet too. As it seems the MT7628 PCIe is based on MT7621 PCIe, I went for an MT7621 datasheet, but sadly in the datasheet the PCIe section is missing completely. Does anybody have a working MT7621/28 bus master setup or a more completed datasheet? I would like to get some information for fixing the mt7620 PCIe driver. It is possible the MSI/bus master is controlled by the undocumented bridge registers (in the pci-mt7621 they controls the manual oscillator settings, I've found a link quality register at 0x101490c4) or in a PCI config space of the root complex (around 0x700 offset). If you have a working SoC with MSI/bus mastering (= mem access from card), can you send me the dump of there spaces? Thanks best regards, Petr