From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88459C133; Wed, 27 Aug 2025 06:51:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756277494; cv=none; b=hUO9X5gDHOF0SuksHDXuDhVZNyNHEMkBZOXirsl2/ZzPojXnHRGCdgde1tlbZHRmMRZ0IwnhGdBDM/rE8DtJfKwlm67f5wLutdmn41tMbPbJDDbPcxOwOjeRGvZxidMsfVNl9KONMYnst17ThXnmHRRiXP8ItwLxvUioZljo5UI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756277494; c=relaxed/simple; bh=6n/bITa6vrmP6YxQjYpYAvl0pURUaNYm8xkK9JCAWa8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=igsb6r6SMzmgygpw9SXboPfAichMZeUCD61X7Kz1dW+dFxFJA+o6qXQbywbF/8X5FZS8MgPacfWplniQCuxNVfPS3mjYCB3kNBTujs2z23NgfTClzdDDLXC7yZbbQaUvnL9CRkU7VfLVgaUPrcG9RzGM7K0qsNHik/5CD/6/4bc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=noD4En54; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="noD4En54" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Type:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To; bh=6n/bITa6vrmP6YxQjYpYAvl0pURUaNYm8xkK9JCAWa8=; b=noD4En545Nt/MdX0PP6isfTCIm nzzsDKAnZVdX0JQAaI/cY0hmmj4qQ34OFnMnfj7gzvR749DUPsZVAeEENOUrNf8dKgsSdc1dL40yU +d0TrjSv0RRgNY4vGdZsMDDw25760fIzo77/LhnS574eAc0b5k+ORFfbAiN0RQPdenFMW+P8Z1X9w 5GFOcifgnTV1kJ/hZzz9Wlnp5vsuXy09PlBO/bUJw83SEhZ8NgZ7fQnv+H1Wb5sUceVheNheVV1RY MjHOsf+fHlCaRlT+ByUybYdRFVjjL0KSbnpcQBFbT7Qz3xhL8DPpssadKJbxiZpdtux/aYJKbb+4B VxCNnEnw==; Received: from [213.244.170.152] (helo=phil.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ur9ze-0005xU-Cd; Wed, 27 Aug 2025 08:50:50 +0200 From: Heiko Stuebner To: Yury Norov , Rasmus Villemoes , Jaehoon Chung , Ulf Hansson , Shreeya Patel , Mauro Carvalho Chehab , Sandy Huang , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Vinod Koul , Kishon Vijay Abraham I , Nicolas Frattaroli , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Shawn Lin , Lorenzo Pieralisi , Krzysztof =?UTF-8?B?V2lsY3p5xYRza2k=?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Chanwoo Choi , MyungJoo Ham , Kyungmin Park , Qin Jian , Michael Turquette , Stephen Boyd , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , Nicolas Frattaroli Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, linux-sound@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-pci@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, llvm@lists.linux.dev, Nicolas Frattaroli Subject: Re: [PATCH v3 01/20] bitmap: introduce hardware-specific bitfield operations Date: Wed, 27 Aug 2025 08:50:49 +0200 Message-ID: <9063025.MhkbZ0Pkbq@phil> In-Reply-To: <20250825-byeword-update-v3-1-947b841cdb29@collabora.com> References: <20250825-byeword-update-v3-0-947b841cdb29@collabora.com> <20250825-byeword-update-v3-1-947b841cdb29@collabora.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Am Montag, 25. August 2025, 10:28:21 Mitteleurop=C3=A4ische Sommerzeit schr= ieb Nicolas Frattaroli: > Hardware of various vendors, but very notably Rockchip, often uses > 32-bit registers where the upper 16-bit half of the register is a > write-enable mask for the lower half. >=20 > This type of hardware setup allows for more granular concurrent register > write access. >=20 > Over the years, many drivers have hand-rolled their own version of this > macro, usually without any checks, often called something like > HIWORD_UPDATE or FIELD_PREP_HIWORD, commonly with slightly different > semantics between them. >=20 > Clearly there is a demand for such a macro, and thus the demand should > be satisfied in a common header file. As this is a convention that spans > across multiple vendors, and similar conventions may also have > cross-vendor adoption, it's best if it lives in a vendor-agnostic header > file that can be expanded over time. >=20 > Add hw_bitfield.h with two macros: FIELD_PREP_WM16, and > FIELD_PREP_WM16_CONST. The latter is a version that can be used in > initializers, like FIELD_PREP_CONST. >=20 > Suggested-by: Yury Norov [NVIDIA] > Signed-off-by: Nicolas Frattaroli Acked-by: Heiko Stuebner