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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Qiang Yu <quic_qianyu@quicinc.com>,
	Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
	Ziyue Zhang <quic_ziyuzhan@quicinc.com>
Cc: lpieralisi@kernel.org, kwilczynski@kernel.org,
	manivannan.sadhasivam@linaro.org, robh@kernel.org,
	bhelgaas@google.com, krzk+dt@kernel.org,
	neil.armstrong@linaro.org, abel.vesa@linaro.org, kw@linux.com,
	conor+dt@kernel.org, vkoul@kernel.org, kishon@kernel.org,
	andersson@kernel.org, konradybcio@kernel.org,
	linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, quic_krichai@quicinc.com,
	quic_vbadigan@quicinc.com
Subject: Re: [PATCH v1 2/4] dt-bindings: PCI: qcom,pcie-sa8775p: document link_down reset
Date: Wed, 4 Jun 2025 13:36:05 +0200	[thread overview]
Message-ID: <9089f618-0df1-4710-8158-36f58c94a0c6@kernel.org> (raw)
In-Reply-To: <43a6e141-adab-42e9-9966-ec54cb91a6de@quicinc.com>

On 04/06/2025 12:05, Qiang Yu wrote:
>>>>> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
>>>>> ---
>>>>>   .../devicetree/bindings/pci/qcom,pcie-sa8775p.yaml  | 13 +++++++++----
>>>>>   1 file changed, 9 insertions(+), 4 deletions(-)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
>>>>> index e3fa232da2ca..805258cbcf2f 100644
>>>>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
>>>>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
>>>>> @@ -61,11 +61,14 @@ properties:
>>>>>         - const: global
>>>>>     resets:
>>>>> -    maxItems: 1
>>>>> +    minItems: 1
>>>>> +    maxItems: 2
>>>> Shouldn't we just update this to maxItems:2 / minItems:2 and drop
>>>> minItems:1 from the next clause?
>>> Hi Dmitry,
>>>
>>> link_down reset is optional. In many other platforms, like sm8550
>>> and x1e80100, link_down reset is documented as a optional reset.
>>> PCIe will works fine without link_down reset. So I think setting it
>>> as optional is better.
>> You are describing a hardware. How can a reset be optional in the
>> _hardware_? It's either routed or not.
> 
> I feel a bit confused. According to the theory above, everything seems to
> be non-optional when describing hardware, such as registers, clocks,
> resets, regulators, and interrupts—all of them either exist or do not.

Can you construct a DTS being fully complete and correct picture of
hardware without these? If not, they are not optional, because correct
hardware representation would need them.

> 
> Seems like I misunderstand the concept of 'optional'? Is 'optional' only
> used for compatibility across different platforms?
> 
> Additionally, we have documented the PCIe global interrupt as optional. I
> was taught that, in the PCIe driver, this interrupt is retrieved using the
> platform_get_irq_byname_optional API, so it can be documented as optional.
> However, this still seems to contradict the theory mentioned earlier.

ABI is just one side of the required properties.



Best regards,
Krzysztof

  reply	other threads:[~2025-06-04 11:37 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-29  3:54 [PATCH v1 0/4] pci: qcom: drop unrelated clock and add link_down reset for sa8775p Ziyue Zhang
2025-05-29  3:54 ` [PATCH v1 1/4] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings " Ziyue Zhang
2025-05-29  3:54 ` [PATCH v1 2/4] dt-bindings: PCI: qcom,pcie-sa8775p: document link_down reset Ziyue Zhang
2025-06-03 13:11   ` Dmitry Baryshkov
2025-06-04  7:58     ` Ziyue Zhang
2025-06-04  9:15       ` Dmitry Baryshkov
2025-06-04 10:02         ` Qiang Yu
2025-06-04 10:05         ` Qiang Yu
2025-06-04 11:36           ` Krzysztof Kozlowski [this message]
2025-06-04 13:19           ` Dmitry Baryshkov
2025-05-29  3:54 ` [PATCH v1 3/4] arm64: dts: qcom: sa8775p: remove aux clock from pcie phy Ziyue Zhang
2025-05-29  3:54 ` [PATCH v1 4/4] arm64: dts: qcom: sa8775p: add link_down reset for pcie Ziyue Zhang

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