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Fri, 18 Apr 2025 20:26:17 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFGFQuCH0Hqv/o7D1MGakoSD3kUocpcRzFOi91EMpflA/r7ry2B6ULUOaFQPjIvPY054X+fQQ== X-Received: by 2002:a17:902:e5cc:b0:223:3630:cd32 with SMTP id d9443c01a7336-22c5365eaefmr73290615ad.53.1745033177502; Fri, 18 Apr 2025 20:26:17 -0700 (PDT) Received: from [192.168.29.92] ([49.43.228.124]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50eb5354sm24231455ad.154.2025.04.18.20.26.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Apr 2025 20:26:17 -0700 (PDT) Message-ID: <91549089-f66b-8e2c-9708-d880f3bf1a0c@oss.qualcomm.com> Date: Sat, 19 Apr 2025 08:56:08 +0530 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v5 0/9] PCI: Enable Power and configure the TC9563 PCIe switch Content-Language: en-US To: Bjorn Helgaas Cc: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , chaitanya chundru , Bjorn Andersson , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org, Jingoo Han , Bartosz Golaszewski , quic_vbadigan@quicnic.com, amitk@kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, jorge.ramirez@oss.qualcomm.com, Dmitry Baryshkov , Bartosz Golaszewski References: <20250418200056.GA82278@bhelgaas> From: Krishna Chaitanya Chundru In-Reply-To: <20250418200056.GA82278@bhelgaas> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: YU0Lr4ZcdtkdwQ2Sp7Htl0EnYZpDCDSC X-Authority-Analysis: v=2.4 cv=RbSQC0tv c=1 sm=1 tr=0 ts=680317da cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=M6NtEvFuFW5htA+UmNA0rQ==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=MuaoRvlZ_d6aMCo3pHsA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: YU0Lr4ZcdtkdwQ2Sp7Htl0EnYZpDCDSC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-19_01,2025-04-17_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 suspectscore=0 adultscore=0 impostorscore=0 clxscore=1015 bulkscore=0 phishscore=0 priorityscore=1501 spamscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504190026 On 4/19/2025 1:30 AM, Bjorn Helgaas wrote: > On Sat, Apr 12, 2025 at 07:19:49AM +0530, Krishna Chaitanya Chundru wrote: >> TC9563 is the PCIe switch which has one upstream and three downstream >> ports. To one of the downstream ports ethernet MAC is connected as endpoint >> device. Other two downstream ports are supposed to connect to external >> device. One Host can connect to TC956x by upstream port. > > I guess this topology is for one specific platform that includes the > TC9563? Since it's a PCIe switch, I assume it could also be used in > other platforms with other topologies? > This topology is for the switch not for per platform, the switch exposes two DSP's for external device and one DSP has always integrated MAC. >> TC9563 switch power is controlled by the GPIO's. After powering on >> the switch will immediately participate in the link training. if the >> host is also ready by that time PCIe link will established. >> >> The TC9563 needs to configured certain parameters like de-emphasis, >> disable unused port etc before link is established. >> >> As the controller starts link training before the probe of pwrctl driver, >> the PCIe link may come up as soon as we power on the switch. Due to this >> configuring the switch itself through i2c will not have any effect as >> this configuration needs to done before link training. To avoid this >> introduce two functions in pci_ops to start_link() & stop_link() which >> will disable the link training if the PCIe link is not up yet. >> >> This series depends on the https://lore.kernel.org/all/20250124101038.3871768-3-krishna.chundru@oss.qualcomm.com/ > > How so? > https://lore.kernel.org/all/20250124101038.3871768-3-krishna.chundru@oss.qualcomm.com/ > adds a schema "n-fts" property, but this series doesn't mention > "n-fts". This series *does* add this: > > of_property_read_u8_array(node, "nfts", cfg->nfts, 2); > > Is that supposed to be the same thing, or does "nfts" magically match > "n-fts"? > It is miss from my side, thanks for pointing out, I will fix this in next patch series. - Krishna Chaitanya. > Bjorn