From: Vidya Sagar <vidyas@nvidia.com>
To: Andrew Murray <andrew.murray@arm.com>
Cc: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<robh+dt@kernel.org>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <kishon@ti.com>,
<gustavo.pimentel@synopsys.com>, <digetx@gmail.com>,
<mperttunen@nvidia.com>, <linux-pci@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
<mmaddireddy@nvidia.com>, <sagar.tv@gmail.com>
Subject: Re: [PATCH 6/6] PCI: tegra: Add support to enable slot regulators
Date: Tue, 27 Aug 2019 21:54:17 +0530 [thread overview]
Message-ID: <91f8914a-22a9-8b7c-bc00-c309a21d83db@nvidia.com> (raw)
In-Reply-To: <20190827154725.GP14582@e119886-lin.cambridge.arm.com>
On 8/27/2019 9:17 PM, Andrew Murray wrote:
> On Mon, Aug 26, 2019 at 01:01:43PM +0530, Vidya Sagar wrote:
>> Add support to get regulator information of 3.3V and 12V supplies of a PCIe
>> slot from the respective controller's device-tree node and enable those
>> supplies. This is required in platforms like p2972-0000 where the supplies
>> to x16 slot owned by C5 controller need to be enabled before attempting to
>> enumerate the devices.
>>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> ---
>> drivers/pci/controller/dwc/pcie-tegra194.c | 65 ++++++++++++++++++++++
>> 1 file changed, 65 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>> index 8a27b25893c9..97de2151a738 100644
>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -278,6 +278,8 @@ struct tegra_pcie_dw {
>> u32 aspm_l0s_enter_lat;
>>
>> struct regulator *pex_ctl_supply;
>> + struct regulator *slot_ctl_3v3;
>> + struct regulator *slot_ctl_12v;
>>
>> unsigned int phy_count;
>> struct phy **phys;
>> @@ -1047,6 +1049,59 @@ static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)
>> }
>> }
>>
>> +static void tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie)
>> +{
>> + pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3");
>> + if (IS_ERR(pcie->slot_ctl_3v3))
>> + pcie->slot_ctl_3v3 = NULL;
>> +
>> + pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v");
>> + if (IS_ERR(pcie->slot_ctl_12v))
>> + pcie->slot_ctl_12v = NULL;
>
> Do these need to take into consideration -EPROBE_DEFER?
Since these are devm_* APIs, isn't it taken care of automatically?
>
> Thanks,
>
> Andrew Murray
>
>> +}
>> +
>> +static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie)
>> +{
>> + int ret;
>> +
>> + if (pcie->slot_ctl_3v3) {
>> + ret = regulator_enable(pcie->slot_ctl_3v3);
>> + if (ret < 0) {
>> + dev_err(pcie->dev,
>> + "Failed to enable 3V3 slot supply: %d\n", ret);
>> + return ret;
>> + }
>> + }
>> +
>> + if (pcie->slot_ctl_12v) {
>> + ret = regulator_enable(pcie->slot_ctl_12v);
>> + if (ret < 0) {
>> + dev_err(pcie->dev,
>> + "Failed to enable 12V slot supply: %d\n", ret);
>> + if (pcie->slot_ctl_3v3)
>> + regulator_disable(pcie->slot_ctl_3v3);
>> + return ret;
>> + }
>> + }
>> +
>> + /*
>> + * According to PCI Express Card Electromechanical Specification
>> + * Revision 1.1, Table-2.4, T_PVPERL (Power stable to PERST# inactive)
>> + * should be a minimum of 100ms.
>> + */
>> + msleep(100);
>> +
>> + return 0;
>> +}
>> +
>> +static void tegra_pcie_disable_slot_regulators(struct tegra_pcie_dw *pcie)
>> +{
>> + if (pcie->slot_ctl_12v)
>> + regulator_disable(pcie->slot_ctl_12v);
>> + if (pcie->slot_ctl_3v3)
>> + regulator_disable(pcie->slot_ctl_3v3);
>> +}
>> +
>> static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
>> bool en_hw_hot_rst)
>> {
>> @@ -1060,6 +1115,10 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
>> return ret;
>> }
>>
>> + ret = tegra_pcie_enable_slot_regulators(pcie);
>> + if (ret < 0)
>> + goto fail_slot_reg_en;
>> +
>> ret = regulator_enable(pcie->pex_ctl_supply);
>> if (ret < 0) {
>> dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret);
>> @@ -1142,6 +1201,8 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
>> fail_core_clk:
>> regulator_disable(pcie->pex_ctl_supply);
>> fail_reg_en:
>> + tegra_pcie_disable_slot_regulators(pcie);
>> +fail_slot_reg_en:
>> tegra_pcie_bpmp_set_ctrl_state(pcie, false);
>>
>> return ret;
>> @@ -1174,6 +1235,8 @@ static int __deinit_controller(struct tegra_pcie_dw *pcie)
>> return ret;
>> }
>>
>> + tegra_pcie_disable_slot_regulators(pcie);
>> +
>> ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false);
>> if (ret) {
>> dev_err(pcie->dev, "Failed to disable controller %d: %d\n",
>> @@ -1372,6 +1435,8 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
>> return ret;
>> }
>>
>> + tegra_pcie_get_slot_regulators(pcie);
>> +
>> pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl");
>> if (IS_ERR(pcie->pex_ctl_supply)) {
>> dev_err(dev, "Failed to get regulator: %ld\n",
>> --
>> 2.17.1
>>
next prev parent reply other threads:[~2019-08-27 16:24 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-26 7:31 [PATCH 0/6] PCI: tegra: Enable PCIe C5 controller of Tegra194 in p2972-0000 platform Vidya Sagar
2019-08-26 7:31 ` [PATCH 1/6] dt-bindings: PCI: tegra: Add sideband pins configuration entries Vidya Sagar
2019-08-26 7:31 ` [PATCH 2/6] arm64: tegra: Add configuration for PCIe C5 sideband signals Vidya Sagar
2019-08-26 7:31 ` [PATCH 3/6] PCI: tegra: Add support to configure sideband pins Vidya Sagar
2019-08-27 15:30 ` Andrew Murray
2019-08-27 15:40 ` Vidya Sagar
2019-08-26 7:31 ` [PATCH 4/6] dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries Vidya Sagar
2019-08-26 7:31 ` [PATCH 5/6] arm64: tegra: Add PCIe slot supply information in p2972-0000 platform Vidya Sagar
2019-08-26 7:31 ` [PATCH 6/6] PCI: tegra: Add support to enable slot regulators Vidya Sagar
2019-08-27 15:47 ` Andrew Murray
2019-08-27 16:24 ` Vidya Sagar [this message]
2019-08-27 17:13 ` Andrew Murray
2019-08-28 9:07 ` Thierry Reding
2019-08-28 9:37 ` Andrew Murray
2019-08-28 9:10 ` [PATCH 0/6] PCI: tegra: Enable PCIe C5 controller of Tegra194 in p2972-0000 platform Thierry Reding
2019-08-28 10:04 ` Vidya Sagar
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