Re: [PATCH v2 2/3] PCI: tegra194: Reset BARs when running in PCIe endpoint mode

[Manikanta Maddireddy <mmaddireddy@nvidia.com>]

On 09/02/26 11:57 pm, Niklas Cassel wrote:

> On Sun, Feb 08, 2026 at 11:41:42PM +0530, Manikanta Maddireddy wrote:
>> Hi Niklas,
>>
>> Tegra PCIe exposes only DMA register over BAR4, not iATU.
>> So, the issue described in this commit message is not applicable.
>> This patch is disabling BAR2 and BAR4, after enumeration I see
>> only BAR0. I think we should revert this patch.
>> Please share your inputs on this.
> If you look at this commit, it only disables all BARs by default,
> which brings the tegra driver in-line with all other DWC based
> endpoint drivers: dra7xx, imx6, layerscape-ep, artpec6, dw-rockchip,
> qcom-ep, rcar-gen4, and uniphier-ep.
>
> A PCI endpoint function (EPF) driver will still be able to enable a
> BAR that was disabled in .init().
> However, an EPF driver will not be able to use/enable a reserved BAR.
>
> Look at e.g. the code in pci-epf-test. It will not allocate backing
> memory for a BAR that is reserved, so having a BAR enabled that we
> have not allocated backing memory for is wrong.
>
> Commit c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint
> mode in Tegra194") is the commit that marked all BARs other than
> BAR0 as reserved, so if you want to test BARs other than BAR0,
> talk to the author of that commit.
>
> If you revert this patch, tools/testing/selftests/pci_endpoint/pci_endpoint_test
> will once again fail the consecutive BAR test, so I think it would
> be wrong to revert this patch.
>
> If it is ATU registers or eDMA registers exposed in BAR4 does not
> really matter. The end result is that you overwrite eDMA registers
> that you should not be overwriting when you run the BAR tests.
> (So BAR4 should absolutely be marked as reserved).
>
> I don't recall, but if you overwrite the eDMA registers, then in
> addition to the consecutive BAR test failing, most likely the DMA
> test cases will also fail.
>
> Have you tried running
> tools/testing/selftests/pci_endpoint/pci_endpoint_test
> ?
>
>
> Kind regards,
> Niklas

Hi Niklas,

In Tegra234 PCIe, BAR1 is MSI-X table and BAR2 is DMA registers backed

by PCIe HW RAM and registers. EPF driver shouldn't allocate memory for

these two BARs. This is the reason for marking them as reserved in

Tegra PCIe driver. DMA registers are exposed over BAR2 to allow

PCI client driver in host to transfer data from host to endpoint

using endpoint remote DMA read functionality. BAR test fails on this

because not all register bits are writable. Consider NVMe example

which has RO capability bits at the start of the BAR, it is not correct

to add BAR test on these bits.


I think following fixes are required to address this issue,

1. BAR test in pci_endpoint_test should skip MSI-X table.

2. BAR test in pci_endpoint_test should provide option to

skip this test on known reserved BARs, maybe we can use

pci_endpoint_test_data for this.

3. EPC driver should provide BAR_DISABLED enum to disable

unused BARs.

4. Tegra PCIe driver should disable only BAR_DISABLED bars and

leave BAR_RESERVED untouched.

5. Return NO_BAR for both BAR_DISABLED and BAR_RESERVED in

pci_epc_get_next_free_bar()


Let me know your opinion on this.