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Sun, 8 Mar 2026 23:49:02 -0500 Message-ID: <95b73073-5a94-4e69-820c-7154be72056a@ti.com> Date: Mon, 9 Mar 2026 10:19:01 +0530 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/2] PCI: dwc: ep: Fix MSI-X configuration to write to correct physical function To: Bjorn Helgaas CC: "linux-pci@vger.kernel.org" , "jingoohan1@gmail.com" , "mani@kernel.org" , "lpieralisi@kernel.org" , "kwilczynski@kernel.org" , "robh@kernel.org" , "bhelgaas@google.com" , "yoshihiro.shimoda.uh@renesas.com" , "fancer.lancer@gmail.com" , "Zhiqiang.Hou@nxp.com" , "gustavo.pimentel@synopsys.com" , "cassel@kernel.org" , "linux-kernel@vger.kernel.org" , "Vadapalli, Siddharth" , "Anwar, Md Danish" References: <20260306184519.GA131984@bhelgaas> Content-Language: en-US From: Aksh Garg In-Reply-To: <20260306184519.GA131984@bhelgaas> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001708F:EE_|CH2PR10MB4373:EE_ X-MS-Office365-Filtering-Correlation-Id: 24ea8ccf-24b5-4392-3a27-08de7d9732a6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|7416014|376014; X-Microsoft-Antispam-Message-Info: hLAs12yBXgB9cUzkzQNTVhr96Re7hEzPo8Vf74csE9C50LM0Y/YPSNRzxywHjwCJWpTFVDHavSciIQuzZH1BOb+hY9HlwKnQSuZGU0LzecPa3tDTSS9aH+w3zxpMbvRicPzCZiIlukZ4Rt75ysmfMTic6sKXH/nZQjlVEopxYLHkSTZMBSQW2AHc/uRt9vjX39c50/TRiwmgK6ycumh339mw5PDUxF5a3FrAiRIs5c1BQtRXgAp4MwxjG0olXZuMbIh0ZWq520U5VAnVcPe7mzO9a9JARU/CgtdsnsG1fbHDswiJYp6VQ1IVszRLZ03t4AcFBMzMl/ARBRKcXV0MxLzlBiAxJFCWg9ae/CvykXr/Rlu0zTIdcW8aIp4oLDfOYG1BANONAZLWvOh/B1CsWGirnTS1rbJGZL9om8UqQue/MbtxdlMyA3tT8ZLxvA5bgh4h0lmtO5sHG00BDtjuEO+6aRAgMmRUw4TJXCcDAulbcWC4IF8vkDC9Cmd4GoJbKGKcCMXM4zdxvCb9Ob80KanYpImep9RMe+khReJrJA6RTFqCzsVEnaTb0NRQxgW9yfhyKIS/8IDxtoRAlBZjVvNGJ50LmjEkuJhhRcY7yEqvxIE1rSGkPUHr8LhryUMPapsg2xRGsa4THSEv2M7ndLg/tLcvLktCc9Qx7/+7RXSdLqLxJ8tr+DoSfxB+sD6OPWQgdVsUxW4kPg7fQMzOLabmivs+vme2AdcpoBhUYj4= X-Forefront-Antispam-Report: CIP:198.47.21.195;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:flwvzet201.ext.ti.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(7416014)(376014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: K1FR8b0XSapgPvM1lEw55Fc95t7GavsiuSFp/Kx9ozxYkMFkwVXIKB10SIcIT+wqXG0K53V3nSaftinFmpwGIKt99H7No+9DGlXZRH4ClhgiK+VO8bgTAvB5H9kE3M5x0TV3dBIZic4ilZG4rj4mZmj4jvDZfkAxFi/A5+jQ26d/NmqGCAr76N8PVEog2nAINwSl8htZ7lWd0Q1wCPDEeK1xCQwkdf1mKsTJREwBIdvNQRymCGRg/6TE7jdZVa0Uk86hNkJPoINy+V62I0NqCaRiaPgRTz8J4o5iDgGILB5r6Uu4BbH0f12Sb3ORqCcByppeL6fnBgqqn6MXB4cisK4CkasKVTp7giddJw/kDiL5asiTD/xJbJOtJ9gE7nzk6BCzlOJGJ/84MWHyR99aiYSeI+AiTxdCoUhhp1PhYfjUrn5X9S417RgQuzdVu6E4 X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2026 04:49:07.5474 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 24ea8ccf-24b5-4392-3a27-08de7d9732a6 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001708F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR10MB4373 On 07/03/26 00:15, Bjorn Helgaas wrote: > On Tue, Feb 24, 2026 at 02:08:16PM +0530, Aksh Garg wrote: >> The MSI-X configuration code reads from the correct physical function's >> register space using dw_pcie_ep_readw_dbi(), but writes back only to >> PF0 using the old dw_pcie_writew_dbi() helper. This causes incorrect >> MSI-X configuration for other PFs. >> >> Fix this by using dw_pcie_ep_writew_dbi() to write to the correct PF's >> register space, matching the read operation. > > Is this another case of using "PF" in a non-SR-IOV context, as I asked > about here? > > https://lore.kernel.org/all/20260223185558.GA3701139@bhelgaas > > I do not want to use "PF" unless we're talking about a device with an > SR-IOV Capability and we're doing something specific to SR-IOV. I apologize to commit the same mistake here after your feedback. While posting this series again, I made changes to patch 2/2, but forgot to look at the commit message for this patch. > >> Fixes: 70fa02ca1446 ("PCI: dwc: Add dw_pcie_ep_{read,write}_dbi[2] helpers") >> Reviewed-by: Niklas Cassel >> Signed-off-by: Aksh Garg >> --- >> >> Changes since v1: >> - None >> >> v1: https://lore.kernel.org/all/20260202072758.101845-2-a-garg7@ti.com/ >> >> drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c >> index 7e7844ff0f7e..771241e1a2c9 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c >> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c >> @@ -745,7 +745,7 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no, >> val = dw_pcie_ep_readw_dbi(ep, func_no, reg); >> val &= ~PCI_MSIX_FLAGS_QSIZE; >> val |= nr_irqs - 1; /* encoded as N-1 */ >> - dw_pcie_writew_dbi(pci, reg, val); >> + dw_pcie_ep_writew_dbi(ep, func_no, reg, val); >> >> reg = ep_func->msix_cap + PCI_MSIX_TABLE; >> val = offset | bir; >> -- >> 2.34.1 >>