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b=tN1SJa9LYmn5mbatocJMbOta0jCTnLTSr9h6DCsnmYt2kAVmQsmFZFKViDtRj80utfUwNXk+Gx6swy01xabRqillZxP+IX0Zl5UC4EVDFNm/mvQnjpO2KDQlpIAUmfN8gWM2QqZX/WWMuF66mfktjVHBnfAzLd2h6C62kY8UgvY= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from DS0PR12MB6390.namprd12.prod.outlook.com (2603:10b6:8:ce::7) by IA0PR12MB9047.namprd12.prod.outlook.com (2603:10b6:208:402::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8606.32; Mon, 7 Apr 2025 14:25:35 +0000 Received: from DS0PR12MB6390.namprd12.prod.outlook.com ([fe80::38ec:7496:1a35:599f]) by DS0PR12MB6390.namprd12.prod.outlook.com ([fe80::38ec:7496:1a35:599f%5]) with mapi id 15.20.8606.033; Mon, 7 Apr 2025 14:25:35 +0000 Message-ID: <97a53556-4e01-40ed-80da-0369f401ceda@amd.com> Date: Mon, 7 Apr 2025 09:25:31 -0500 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 16/16] CXL/PCI: Disable CXL protocol errors during CXL Port cleanup To: Jonathan Cameron Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, nifan.cxl@gmail.com, dave@stgolabs.net, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com, dan.j.williams@intel.com, bhelgaas@google.com, mahesh@linux.ibm.com, ira.weiny@intel.com, oohall@gmail.com, Benjamin.Cheatham@amd.com, rrichter@amd.com, nathan.fontenot@amd.com, Smita.KoralahalliChannabasappa@amd.com, lukas@wunner.de, ming.li@zohomail.com, PradeepVineshReddy.Kodamati@amd.com References: <20250327014717.2988633-1-terry.bowman@amd.com> <20250327014717.2988633-17-terry.bowman@amd.com> <20250404180427.00007602@huawei.com> Content-Language: en-US From: "Bowman, Terry" In-Reply-To: <20250404180427.00007602@huawei.com> Content-Type: text/plain; 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This can potentialy allow unnecessary interrupt processing on >> behalf of the CXL errors while the device is destroyed. >> >> Disable CXL protocol errors by setting the CXL devices' AER mask register. >> >> Introduce pci_aer_mask_internal_errors() similar to pci_aer_unmask_internal_errors(). >> >> Next, introduce cxl_disable_prot_errors() to call pci_aer_mask_internal_errors(). >> Register cxl_disable_prot_errors() to run at CXL device cleanup. >> Register for CXL Root Ports, CXL Downstream Ports, CXL Upstream Ports, and >> CXL Endpoints. >> >> Signed-off-by: Terry Bowman > A few small comments in here. I haven't looked through all the rest of the series > as out of time today but this one caught my eye. >> >> @@ -223,7 +238,7 @@ static void cxl_endpoint_port_init_ras(struct cxl_port *port) >> struct device *cxlmd_dev __free(put_device) = &cxlmd->dev; >> struct cxl_dev_state *cxlds = cxlmd->cxlds; >> >> - if (!dport || !dev_is_pci(dport->dport_dev)) { >> + if (!dport || !dev_is_pci(dport->dport_dev) || !dev_is_pci(cxlds->dev)) { >> dev_err(&port->dev, "CXL port topology not found\n"); >> return; >> } >> @@ -232,6 +247,7 @@ static void cxl_endpoint_port_init_ras(struct cxl_port *port) >> >> cxl_assign_error_handlers(cxlmd_dev, &cxl_ep_error_handlers); >> cxl_enable_prot_errors(cxlds->dev); >> + devm_add_action_or_reset(cxlds->dev, cxl_disable_prot_errors, cxlds->dev); > This can fail (at least in theory). Should at least scream that oddly we've > disabled error handling interrupts if it is hard to return anything cleanly. > > Same for all the other cases. Ok. I will add a dev_err() for errors returned by devm_add_action_or_reset(). >> } >> >> #else >> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c >> index d3068f5cc767..d1ef0c676ff8 100644 >> --- a/drivers/pci/pcie/aer.c >> +++ b/drivers/pci/pcie/aer.c >> @@ -977,6 +977,31 @@ void pci_aer_unmask_internal_errors(struct pci_dev *dev) >> } >> EXPORT_SYMBOL_NS_GPL(pci_aer_unmask_internal_errors, "CXL"); >> >> +/** >> + * pci_aer_mask_internal_errors - mask internal errors >> + * @dev: pointer to the pcie_dev data structure >> + * >> + * Masks internal errors in the Uncorrectable and Correctable Error >> + * Mask registers. >> + * >> + * Note: AER must be enabled and supported by the device which must be >> + * checked in advance, e.g. with pcie_aer_is_native(). >> + */ >> +void pci_aer_mask_internal_errors(struct pci_dev *dev) >> +{ >> + int aer = dev->aer_cap; >> + u32 mask; >> + >> + pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask); >> + mask |= PCI_ERR_UNC_INTN; >> + pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, mask); >> + > It does an extra clear we don't need, but.... > pci_clear_and_set_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, > 0, PCI_ERR_UNC_INTN); > > is at very least shorter than the above 3 lines. Doing so will overwrite the existing mask. CXL normally only uses AER UIE/CIE but if the device happens to lose alternate training and no longer identifies as a CXL device than this mask value would be critical for reporting PCI AER errors and would need UCE/CE enabled (other than UIE/CIE). -Terry >> + pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask); >> + mask |= PCI_ERR_COR_INTERNAL; >> + pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask); >> +} >> +EXPORT_SYMBOL_NS_GPL(pci_aer_mask_internal_errors, "CXL"); >> + >> static bool is_cxl_mem_dev(struct pci_dev *dev) >> { >> /* >> diff --git a/include/linux/aer.h b/include/linux/aer.h >> index a65fe324fad2..f0c84db466e5 100644 >> --- a/include/linux/aer.h >> +++ b/include/linux/aer.h >> @@ -101,5 +101,6 @@ int cper_severity_to_aer(int cper_severity); >> void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn, >> int severity, struct aer_capability_regs *aer_regs); >> void pci_aer_unmask_internal_errors(struct pci_dev *dev); >> +void pci_aer_mask_internal_errors(struct pci_dev *dev); >> #endif //_AER_H_ >>