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Tue, 06 May 2025 03:11:14 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH8U/guIu0vbzSPfeTmdl89koUVyuEsL/oTZLqYtIdxTjXuLx/PmEC/GmoUm6x6tbynQ691+Q== X-Received: by 2002:a17:902:f682:b0:216:410d:4c53 with SMTP id d9443c01a7336-22e1036be29mr230061015ad.41.1746526273933; Tue, 06 May 2025 03:11:13 -0700 (PDT) Received: from [10.218.37.122] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30a3484bc23sm13457073a91.43.2025.05.06.03.11.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 06 May 2025 03:11:13 -0700 (PDT) Message-ID: <99da4243-3e55-3aa0-5657-5a5d2a4415cd@oss.qualcomm.com> Date: Tue, 6 May 2025 15:41:07 +0530 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v2 2/4] PCI: qcom: Do not enumerate bus before endpoint devices are ready Content-Language: en-US To: Niklas Cassel , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Rob Herring , Bjorn Helgaas , Krishna chaitanya chundru Cc: Wilfred Mallawa , Damien Le Moal , Hans Zhang <18255117159@163.com>, Laszlo Fiat , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org References: <20250506073934.433176-6-cassel@kernel.org> <20250506073934.433176-8-cassel@kernel.org> From: Krishna Chaitanya Chundru In-Reply-To: <20250506073934.433176-8-cassel@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=KcfSsRYD c=1 sm=1 tr=0 ts=6819e043 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=S-OeyO6ZCgE5XVXCpeMA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: D_WQfTL1nlddQPud_fYVaF_Ft-lE8_sM X-Proofpoint-ORIG-GUID: D_WQfTL1nlddQPud_fYVaF_Ft-lE8_sM X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTA2MDA5NyBTYWx0ZWRfX3VLVM8SZ4bKj Jjg7neX0ZxWCqsm605RgrPNiDSa2o79B6ajTCcjvDM2QvC7s4VYb8oUwesk0GNZca77vH0qE54Z HSqIZC8kkDO1kxv5I2Plk8lYHXetrPuLs1mZJLRzzEtVZ9rB9wIAVamHksIW5OUk9GKI87wgEPA FnsBVXf9U453nTpVbOmrMfjg/MhmYu1GXCo00oH7atE2EH+nwtg9wQBvgOOBT5Otr7B+JmZ+2U8 hPP47nhFvnePnGRP8SSDhkFgCAxgXck2oTLrjwR6iGr36NHIGRsGDEemhEfezDmM/Z6soPnGttE QaQ+zzgIqiPWZ4IdDr9DAEJSla3y/jP3d/YXQUouTmJ1jFRfPohTdPgdpJE7JaGCWPD+gfEsujW ZIVBrujvVCQ+AM+wnz4KPvzQmaTnAAthyHgDmNTpMbwTpza+9ZIHujq20FMWEufp3oPP4iyU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-06_04,2025-05-05_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 suspectscore=0 bulkscore=0 mlxlogscore=999 phishscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 adultscore=0 clxscore=1015 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505060097 On 5/6/2025 1:09 PM, Niklas Cassel wrote: > Commit 36971d6c5a9a ("PCI: qcom: Don't wait for link if we can detect Link > Up") changed so that we no longer call dw_pcie_wait_for_link(), and instead > enumerate the bus when receiving a Link Up IRQ. > > Before 36971d6c5a9a, we called dw_pcie_wait_for_link(), and in the first > iteration of the loop, the link will never be up (because the link was just > started), dw_pcie_wait_for_link() will then sleep for LINK_WAIT_SLEEP_MS > (90 ms), before trying again. > > This means that even if a driver was missing a msleep(PCIE_T_RRS_READY_MS) > (100 ms), because of the call to dw_pcie_wait_for_link(), enumerating the > bus would essentially be delayed by that time anyway (because of the sleep > LINK_WAIT_SLEEP_MS (90 ms)). > > While we could add the msleep(PCIE_T_RRS_READY_MS) after deasserting PERST > (qcom already has an unconditional 1 ms sleep after deasserting PERST), > that would essentially bring back an unconditional delay during probe (the > whole reason to use a Link Up IRQ was to avoid an unconditional delay > during probe). > > Thus, add the msleep(PCIE_T_RRS_READY_MS) before enumerating the bus in the > IRQ handler. This way, for qcom SoCs that has a link up IRQ, we will not > have a 100 ms unconditional delay during boot for unpopulated PCIe slots. > > Fixes: 36971d6c5a9a ("PCI: qcom: Don't wait for link if we can detect Link Up") > Signed-off-by: Niklas Cassel Reviewed-by: Krishna Chaitanya Chundru > --- > drivers/pci/controller/dwc/pcie-qcom.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index dc98ae63362d..01a60d1f372a 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1565,6 +1565,7 @@ static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data) > > if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) { > dev_dbg(dev, "Received Link up event. Starting enumeration!\n"); > + msleep(PCIE_T_RRS_READY_MS); > /* Rescan the bus to enumerate endpoint devices */ > pci_lock_rescan_remove(); > pci_rescan_bus(pp->bridge->bus);