From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 969FCECAAD2 for ; Mon, 29 Aug 2022 15:23:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230150AbiH2PXl (ORCPT ); Mon, 29 Aug 2022 11:23:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230144AbiH2PXj (ORCPT ); Mon, 29 Aug 2022 11:23:39 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5157788DC0 for ; Mon, 29 Aug 2022 08:23:38 -0700 (PDT) Received: from gallifrey.ext.pengutronix.de ([2001:67c:670:201:5054:ff:fe8d:eefb] helo=[IPv6:::1]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1oSgbl-0007eP-Sn; Mon, 29 Aug 2022 17:23:25 +0200 Message-ID: <9b2eba50b41e19d3f71a08416b295ba2e7bcc1ee.camel@pengutronix.de> Subject: Re: [PATCH v4 4/6] arm64: dts: imx8mp: Add iMX8MP PCIe support From: Lucas Stach To: Richard Zhu , p.zabel@pengutronix.de, bhelgaas@google.com, lorenzo.pieralisi@arm.com, robh@kernel.org, shawnguo@kernel.org, vkoul@kernel.org, alexander.stein@ew.tq-group.com, marex@denx.de, richard.leitner@linux.dev Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Date: Mon, 29 Aug 2022 17:23:23 +0200 In-Reply-To: <1661760917-9558-5-git-send-email-hongxing.zhu@nxp.com> References: <1661760917-9558-1-git-send-email-hongxing.zhu@nxp.com> <1661760917-9558-5-git-send-email-hongxing.zhu@nxp.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.40.4 (3.40.4-1.fc34) MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2001:67c:670:201:5054:ff:fe8d:eefb X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-pci@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Am Montag, dem 29.08.2022 um 16:15 +0800 schrieb Richard Zhu: > Add i.MX8MP PCIe support. > > Signed-off-by: Richard Zhu > Tested-by: Marek Vasut > Tested-by: Richard Leitner > Tested-by: Alexander Stein > --- > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 46 ++++++++++++++++++++++- > 1 file changed, 45 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > index fe178b7d063c..d11f079fd1f3 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > @@ -5,6 +5,7 @@ > > #include > #include > +#include > #include > #include > #include > @@ -410,7 +411,8 @@ iomuxc: pinctrl@30330000 { > }; > > gpr: iomuxc-gpr@30340000 { > - compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; > + compatible = "fsl,imx8mp-iomuxc-gpr", > + "fsl,imx6q-iomuxc-gpr", "syscon"; I don't like this part. The iomux GPR in the i.MX8M* is not really compatible with the i.MX6Q, so I think it's a pretty bad idea to claim it is. Why can't we have this syscon looked up by phandle, like we discussed in some early version of the i.MX8MM patchset? Sorry, for not catching this on the 8MM submission, I was pretty busy back then. Regards, Lucas > reg = <0x30340000 0x10000>; > }; > > @@ -1084,6 +1086,17 @@ media_blk_ctrl: blk-ctrl@32ec0000 { > #power-domain-cells = <1>; > }; > > + pcie_phy: pcie-phy@32f00000 { > + compatible = "fsl,imx8mp-pcie-phy"; > + reg = <0x32f00000 0x10000>; > + resets = <&src IMX8MP_RESET_PCIEPHY>, > + <&src IMX8MP_RESET_PCIEPHY_PERST>; > + reset-names = "pciephy", "perst"; > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>; > + #phy-cells = <0>; > + status = "disabled"; > + }; > + > hsio_blk_ctrl: blk-ctrl@32f10000 { > compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; > reg = <0x32f10000 0x24>; > @@ -1099,6 +1112,37 @@ hsio_blk_ctrl: blk-ctrl@32f10000 { > }; > }; > > + pcie: pcie@33800000 { > + compatible = "fsl,imx8mp-pcie"; > + reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; > + reg-names = "dbi", "config"; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + bus-range = <0x00 0xff>; > + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ > + <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ > + num-lanes = <1>; > + num-viewport = <4>; > + interrupts = ; > + interrupt-names = "msi"; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0x7>; > + interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; > + fsl,max-link-speed = <3>; > + linux,pci-domain = <0>; > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; > + resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, > + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; > + reset-names = "apps", "turnoff"; > + phys = <&pcie_phy>; > + phy-names = "pcie-phy"; > + status = "disabled"; > + }; > + > gpu3d: gpu@38000000 { > compatible = "vivante,gc"; > reg = <0x38000000 0x8000>;