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Tue, 11 Mar 2025 04:01:40 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFvJShX7YcLtJuvnkvs5xiC1/MxsI3XPL/xg/+Wod3SHY2aB1lbaMeinxu1i1VNUiUbskVt6w== X-Received: by 2002:a17:90b:164f:b0:2fe:a0ac:5fcc with SMTP id 98e67ed59e1d1-2ff7cf3e3eamr20418654a91.34.1741690900084; Tue, 11 Mar 2025 04:01:40 -0700 (PDT) Received: from [10.92.192.202] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693e7388sm10834772a91.35.2025.03.11.04.01.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Mar 2025 04:01:39 -0700 (PDT) Message-ID: <9be6ce8e-f0e2-7226-e900-3a0c2506a16a@oss.qualcomm.com> Date: Tue, 11 Mar 2025 16:31:33 +0530 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v7 2/4] PCI: of: Add API to retrieve equalization presets from device tree To: Manivannan Sadhasivam Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com References: <20250225-preset_v6-v7-0-a593f3ef3951@oss.qualcomm.com> <20250225-preset_v6-v7-2-a593f3ef3951@oss.qualcomm.com> <20250306032250.vzfhznmionz3qkx7@thinkpad> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <20250306032250.vzfhznmionz3qkx7@thinkpad> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: NL7YSAe29BItSoO9Mc1YPufRJdZOH6os X-Authority-Analysis: v=2.4 cv=fZ9Xy1QF c=1 sm=1 tr=0 ts=67d01816 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=OvU543Yhaul-O2FZsO4A:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: NL7YSAe29BItSoO9Mc1YPufRJdZOH6os X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-11_01,2025-03-11_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 phishscore=0 impostorscore=0 adultscore=0 spamscore=0 clxscore=1015 malwarescore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503110073 On 3/6/2025 8:52 AM, Manivannan Sadhasivam wrote: > On Tue, Feb 25, 2025 at 05:15:05PM +0530, Krishna Chaitanya Chundru wrote: >> PCIe equalization presets are predefined settings used to optimize >> signal integrity by compensating for signal loss and distortion in >> high-speed data transmission. >> >> As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates >> of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to >> configure lane equalization presets for each lane to enhance the PCIe >> link reliability. Each preset value represents a different combination >> of pre-shoot and de-emphasis values. For each data rate, different >> registers are defined: for 8.0 GT/s, registers are defined in section >> 7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has >> an extra receiver preset hint, requiring 16 bits per lane, while the >> remaining data rates use 8 bits per lane. >> >> Based on the number of lanes and the supported data rate, this function >> reads the device tree property and stores in the presets structure. >> >> Signed-off-by: Krishna Chaitanya Chundru >> --- >> drivers/pci/of.c | 43 +++++++++++++++++++++++++++++++++++++++++++ >> drivers/pci/pci.h | 27 ++++++++++++++++++++++++++- >> 2 files changed, 69 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/pci/of.c b/drivers/pci/of.c >> index 7a806f5c0d20..9ebe7d0e4e0c 100644 >> --- a/drivers/pci/of.c >> +++ b/drivers/pci/of.c >> @@ -851,3 +851,46 @@ u32 of_pci_get_slot_power_limit(struct device_node *node, >> return slot_power_limit_mw; >> } >> EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); >> + >> +/** >> + * of_pci_get_equalization_presets - Parses the "eq-presets-Ngts" property. >> + * >> + * @dev: Device containing the properties. >> + * @presets: Pointer to store the parsed data. >> + * @num_lanes: Maximum number of lanes supported. >> + * >> + * If the property is present read and store the data in the preset structure >> + * else assign default value 0xff to indicate property is not present. > > 'If the property is present, read and store the data in the @presets structure. > Else, assign a default value of PCI_EQ_RESV.' > >> + * >> + * Return: 0 if the property is not available or successfully parsed; errno otherwise. >> + */ >> +int of_pci_get_equalization_presets(struct device *dev, >> + struct pci_eq_presets *presets, >> + int num_lanes) >> +{ >> + char name[20]; >> + int ret; >> + >> + presets->eq_presets_8gts[0] = PCI_EQ_RESV; >> + ret = of_property_read_u16_array(dev->of_node, "eq-presets-8gts", >> + presets->eq_presets_8gts, num_lanes); >> + if (ret && ret != -EINVAL) { >> + dev_err(dev, "Error reading eq-presets-8gts :%d\n", ret); >> + return ret; >> + } >> + >> + for (int i = 0; i < EQ_PRESET_TYPE_MAX; i++) { >> + presets->eq_presets_Ngts[i][0] = PCI_EQ_RESV; >> + snprintf(name, sizeof(name), "eq-presets-%dgts", 8 << (i + 1)); >> + ret = of_property_read_u8_array(dev->of_node, name, >> + presets->eq_presets_Ngts[i], >> + num_lanes); >> + if (ret && ret != -EINVAL) { >> + dev_err(dev, "Error reading %s :%d\n", name, ret); >> + return ret; >> + } >> + } >> + >> + return 0; >> +} >> +EXPORT_SYMBOL_GPL(of_pci_get_equalization_presets); >> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h >> index 01e51db8d285..c8d44b21ef03 100644 >> --- a/drivers/pci/pci.h >> +++ b/drivers/pci/pci.h >> @@ -9,6 +9,8 @@ struct pcie_tlp_log; >> /* Number of possible devfns: 0.0 to 1f.7 inclusive */ >> #define MAX_NR_DEVFNS 256 >> >> +#define MAX_NR_LANES 16 >> + >> #define PCI_FIND_CAP_TTL 48 >> >> #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ >> @@ -808,6 +810,20 @@ static inline u64 pci_rebar_size_to_bytes(int size) >> >> struct device_node; >> >> +#define PCI_EQ_RESV 0xff >> + >> +enum equalization_preset_type { > > For the sake of completeness, you should add EQ_PRESET_TYPE_8GTS also. You could > skip it while reading the of_property_read_u8_array(). Can we add like this to make parsing logic easier otherwise while deference the presets array we need to subtract -1. currently we are using like this presets[EQ_PRESET_TYPE_16GTS] if we want to keep in same way we need to use like below. EQ_PRESET_TYPE_8GTS, EQ_PRESET_TYPE_16GTS = 0, > >> + EQ_PRESET_TYPE_16GTS, >> + EQ_PRESET_TYPE_32GTS, >> + EQ_PRESET_TYPE_64GTS, >> + EQ_PRESET_TYPE_MAX >> +}; >> + >> +struct pci_eq_presets { >> + u16 eq_presets_8gts[MAX_NR_LANES]; >> + u8 eq_presets_Ngts[EQ_PRESET_TYPE_MAX][MAX_NR_LANES]; >> +}; >> + >> #ifdef CONFIG_OF >> int of_get_pci_domain_nr(struct device_node *node); >> int of_pci_get_max_link_speed(struct device_node *node); >> @@ -822,7 +838,9 @@ void pci_release_bus_of_node(struct pci_bus *bus); >> >> int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); >> bool of_pci_supply_present(struct device_node *np); >> - >> +int of_pci_get_equalization_presets(struct device *dev, >> + struct pci_eq_presets *presets, >> + int num_lanes); >> #else >> static inline int >> of_get_pci_domain_nr(struct device_node *node) >> @@ -867,6 +885,13 @@ static inline bool of_pci_supply_present(struct device_node *np) >> { >> return false; >> } >> + >> +static inline int of_pci_get_equalization_presets(struct device *dev, >> + struct pci_eq_presets *presets, >> + int num_lanes) >> +{ > > Don't you need to initialize presets to PCI_EQ_RESV? > I will update in the next patch. - Krishna Chaitanya. > - Mani >