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Mon, 3 Nov 2025 12:16:41 GMT Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0DE2520040; Mon, 3 Nov 2025 12:16:41 +0000 (GMT) Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CE0C92004B; Mon, 3 Nov 2025 12:16:40 +0000 (GMT) Received: from [9.155.208.229] (unknown [9.155.208.229]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 3 Nov 2025 12:16:40 +0000 (GMT) Message-ID: <9c7c4217171fb56c505dc90b8c73b2ce079207a9.camel@linux.ibm.com> Subject: Re: Q: Usage of pci_enable_atomic_ops_to_root() From: Gerd Bayer To: Bjorn Helgaas , Jay Cornwall , Felix Kuehling Cc: Niklas Schnelle , Alexander Schmidt , netdev , linux-rdma , linux-pci , Gerd Bayer Date: Mon, 03 Nov 2025 13:16:40 +0100 In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2 (3.56.2-2.fc42) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=StmdKfO0 c=1 sm=1 tr=0 ts=69089d2e cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=P-IC7800AAAA:8 a=VwQbUJbxAAAA:8 a=zd2uoN0lAAAA:8 a=NhfhhuvIOumIP2zjjAQA:9 a=QEXdDO2ut3YA:10 a=d3PnA9EDa4IxuAV0gXij:22 a=cPQSjfK2_nFv0Q5t_7PE:22 X-Proofpoint-ORIG-GUID: ZN17-7YZVGaLtNLVDUnB2OaiJz3xyAVx X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTAxMDAxOCBTYWx0ZWRfXy3E9mF+d+g66 aEuwz09GHh5GnSbtWUsVsnLvDxGeqn2djLnEC2aTN5lQyKmCoR35KvH7DhiycCKqT1IcSjAko95 DHQAoYMiEGEV8sVrg4Fbh6XZrSsxm4RnXc+LYJncLsrHom8ZIG6HyFlaLx2B9jxGlVLE1cH6dZ2 KJ6eNKnH0ZvRZc03qI+DGpC8DCf0jpsmhjM4Rt/vF8tLKNyypGzZiGkFPqg0m871LpSvTec4No/ iYnQcqqnp8rHUhbG/VWWoG6YYRMPv+0cfIOkWBd7XUQCCZdl1qT3XZQelk4EOlYbtCXtx96XxC5 drskjcFxxRz93m371OxgfeN/YA8pla/hmPwgn04egz2zhVYI8MJkWpCu43o9hnsJJEsdSCvjLY6 sVB0QSpDo0Xdn5AzHjKqcjehueZ3Tw== X-Proofpoint-GUID: 3hC3jq9j6BMtjqmiq1P1VOSq5wwiUkex X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-03_01,2025-11-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 phishscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 adultscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2511010018 On Fri, 2025-10-24 at 19:18 +0200, Gerd Bayer wrote: > Hi all, >=20 > I stumbled over mlx5's usage of pci_enable_atomic_ops_to_root() at >=20 > https://elixir.bootlin.com/linux/v6.18-rc2/source/drivers/net/ethernet/me= llanox/mlx5/core/main.c#L937 >=20 > and was wondering if its repeated calls with the 3 available sizes gave > it the intended result. >=20 > I assume the intent was to enable requesting AtomicOps only if all > three sizes 32/64/128-bit were supported at the root-complex. However, > pci_enable_atomic_ops_to_root() would enable the request at the PCIe > level, even if just 32-bit sized Ops was supported at the root-complex. Looks like I might just send out an RFC patch for review by the Mellanox/NVidia folks? Not sure if I can find a test-setup for this, though... > So I checked other users in the kernel and found an inconclusive > picture: > The AMD GPU that this was originally introduced for [0] checks for a > combination of two sizes, while a few infiniband/ethernet and the vfio- > pci driver do variations of sequential checks (potentially enabling > requests that they don't want to) >=20 > Now the PCIe Spec Rev. 7.0 has also a mixed bag. Section 6.15.3.1 > mandates for Root Ports: >=20 > > If a Root Port implements any AtomicOp Completer capability for host > > memory access, it must implement all 32-bit and 64-bit AtomicOp > > Completer capabilities. Implementing 128-bit CAS Completer capability > > is optional. >=20 > While this is specific, marking the CAS Op Completions in the 128-bit > variant optional, the Capability bits just specify 128-bit AtomicOps > (all AtomicOps: FetchAdd, Swap, CAS). Strictly interpreted, this would > require root port implementors to announce all-or-nothing of 32/64/128- > bit AtomicOps - which kind of makes the size-granularity of the > capability bits useless - and leave the endpoint device (and its > driver) attempting to use 128-bit CAS in the dark... I guess I need to ask the folks at PCI SIG? > [0]: https://lore.kernel.org/linux-pci/1515113100-4718-1-git-send-email-F= elix.Kuehling@amd.com/ >=20 > Can anybody shed some light on this? > Thank you, > Gerd