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[75.72.117.212]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-43310245c34sm1321815ab.2.2025.10.30.18.37.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 30 Oct 2025 18:37:18 -0700 (PDT) Message-ID: <9e60f7ed-7afc-4151-a301-4a0832b9105f@riscstar.com> Date: Thu, 30 Oct 2025 20:37:16 -0500 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/7] dt-bindings: pci: spacemit: introduce PCIe host controller To: Rob Herring Cc: krzk+dt@kernel.org, conor+dt@kernel.org, bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, dlan@gentoo.org, guodong@riscstar.com, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, spacemit@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org References: <20251030220259.1063792-1-elder@riscstar.com> <20251030220259.1063792-4-elder@riscstar.com> <20251031005718.GA539812-robh@kernel.org> Content-Language: en-US From: Alex Elder In-Reply-To: <20251031005718.GA539812-robh@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 10/30/25 7:58 PM, Rob Herring wrote: > On Thu, Oct 30, 2025 at 05:02:54PM -0500, Alex Elder wrote: >> Add the Device Tree binding for the PCIe root complex found on the >> SpacemiT K1 SoC. This device is derived from the Synopsys Designware >> PCIe IP. It supports up to three PCIe ports operating at PCIe gen 2 >> link speeds (5 GT/sec). One of the ports uses a combo PHY, which is >> typically used to support a USB 3 port. >> >> Signed-off-by: Alex Elder >> --- >> .../bindings/pci/spacemit,k1-pcie-host.yaml | 157 ++++++++++++++++++ >> 1 file changed, 157 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml >> >> diff --git a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml >> new file mode 100644 >> index 0000000000000..58239a155ecc0 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml >> @@ -0,0 +1,157 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-host.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: SpacemiT K1 PCI Express Host Controller >> + >> +maintainers: >> + - Alex Elder >> + >> +description: > >> + The SpacemiT K1 SoC PCIe host controller is based on the Synopsys >> + DesignWare PCIe IP. The controller uses the DesignWare built-in >> + MSI interrupt controller, and supports 256 MSIs. > > Wrap lines at 80. OK. >> + >> +allOf: >> + - $ref: /schemas/pci/snps,dw-pcie.yaml# >> + >> +properties: >> + compatible: >> + const: spacemit,k1-pcie >> + >> + reg: >> + items: >> + - description: DesignWare PCIe registers >> + - description: ATU address space >> + - description: PCIe configuration space >> + - description: Link control registers >> + >> + reg-names: >> + items: >> + - const: dbi >> + - const: atu >> + - const: config >> + - const: link >> + >> + clocks: >> + items: >> + - description: DWC PCIe Data Bus Interface (DBI) clock >> + - description: DWC PCIe application AXI-bus master interface clock >> + - description: DWC PCIe application AXI-bus slave interface clock >> + >> + clock-names: >> + items: >> + - const: dbi >> + - const: mstr >> + - const: slv >> + >> + resets: >> + items: >> + - description: DWC PCIe Data Bus Interface (DBI) reset >> + - description: DWC PCIe application AXI-bus master interface reset >> + - description: DWC PCIe application AXI-bus slave interface reset >> + >> + reset-names: >> + items: >> + - const: dbi >> + - const: mstr >> + - const: slv >> + >> + interrupts: >> + items: >> + - description: Interrupt used for MSIs >> + >> + interrupt-names: >> + const: msi >> + >> + spacemit,apmu: >> + $ref: /schemas/types.yaml#/definitions/phandle-array >> + description: >> + A phandle that refers to the APMU system controller, whose >> + regmap is used in managing resets and link state, along with >> + and offset of its reset control register. >> + items: >> + - items: >> + - description: phandle to APMU system controller >> + - description: register offset >> + >> +patternProperties: >> + '^pcie?@': > > It's always PCIe, so drop the '?'. I'll fix that. > With that, > > Reviewed-by: Rob Herring (Arm) Thanks for the review. -Alex