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X-CSE-ConnectionGUID: FRTC37GwTx61bDOZOzdgeA== X-CSE-MsgGUID: ZiPsjd1PS1S4jQ0W5en2kg== X-IronPort-AV: E=McAfee;i="6800,10657,11564"; a="60387890" X-IronPort-AV: E=Sophos;i="6.18,293,1751266800"; d="scan'208";a="60387890" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Sep 2025 17:02:39 -0700 X-CSE-ConnectionGUID: DKsIGkttRf+tsOwqCsFKzw== X-CSE-MsgGUID: WnrWbHuCStCZHnZK7S0gmA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,293,1751266800"; d="scan'208";a="177860424" Received: from gabaabhi-mobl2.amr.corp.intel.com (HELO [10.125.109.4]) ([10.125.109.4]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Sep 2025 17:02:37 -0700 Message-ID: <9f6c80e1-3da4-4b23-a1be-5e5093ddd210@intel.com> Date: Thu, 25 Sep 2025 17:02:36 -0700 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v12 10/25] CXL/AER: Update PCI class code check to use FIELD_GET() To: Terry Bowman , dave@stgolabs.net, jonathan.cameron@huawei.com, alison.schofield@intel.com, dan.j.williams@intel.com, bhelgaas@google.com, shiju.jose@huawei.com, ming.li@zohomail.com, Smita.KoralahalliChannabasappa@amd.com, rrichter@amd.com, dan.carpenter@linaro.org, PradeepVineshReddy.Kodamati@amd.com, lukas@wunner.de, Benjamin.Cheatham@amd.com, sathyanarayanan.kuppuswamy@linux.intel.com, linux-cxl@vger.kernel.org, alucerop@amd.com, ira.weiny@intel.com Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org References: <20250925223440.3539069-1-terry.bowman@amd.com> <20250925223440.3539069-11-terry.bowman@amd.com> Content-Language: en-US From: Dave Jiang In-Reply-To: <20250925223440.3539069-11-terry.bowman@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 9/25/25 3:34 PM, Terry Bowman wrote: > Update the AER driver's is_cxl_mem_dev() to use FIELD_GET() while checking > for a CXL Endpoint class code. > > Introduce a genmask bitmask for checking PCI class codes and locate in > include/uapi/linux/pci_regs.h. > > Update the function documentation to reference the latest CXL > specification. > > Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang > > --- > > Changes in v11->v12: > > Changes in v10->v11: > - Add #include to cxl_ras.c > - Removed line wrapping at "(CXL 3.2, 8.1.12.1)". > --- > drivers/pci/pcie/aer.c | 1 + > drivers/pci/pcie/aer_cxl_rch.c | 6 +++--- > include/uapi/linux/pci_regs.h | 2 ++ > 3 files changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c > index befa73ace9bb..6ba8f84add70 100644 > --- a/drivers/pci/pcie/aer.c > +++ b/drivers/pci/pcie/aer.c > @@ -30,6 +30,7 @@ > #include > #include > #include > +#include > #include > #include > #include > diff --git a/drivers/pci/pcie/aer_cxl_rch.c b/drivers/pci/pcie/aer_cxl_rch.c > index bfe071eebf67..c3e2d4cbe8cc 100644 > --- a/drivers/pci/pcie/aer_cxl_rch.c > +++ b/drivers/pci/pcie/aer_cxl_rch.c > @@ -17,10 +17,10 @@ static bool is_cxl_mem_dev(struct pci_dev *dev) > return false; > > /* > - * CXL Memory Devices must have the 502h class code set (CXL > - * 3.0, 8.1.12.1). > + * CXL Memory Devices must have the 502h class code set > + * (CXL 3.2, 8.1.12.1). > */ > - if ((dev->class >> 8) != PCI_CLASS_MEMORY_CXL) > + if (FIELD_GET(PCI_CLASS_CODE_MASK, dev->class) != PCI_CLASS_MEMORY_CXL) > return false; > > return true; > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index bd03799612d3..802a7384f99a 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -73,6 +73,8 @@ > #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ > #define PCI_CLASS_DEVICE 0x0a /* Device class */ > > +#define PCI_CLASS_CODE_MASK __GENMASK(23, 8) > + > #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ > #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ > #define PCI_HEADER_TYPE 0x0e /* 8 bits */