From: valmiki <valmikibow@gmail.com>
To: Marc Zyngier <marc.zyngier@arm.com>,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org
Cc: helgaas@kernel.org, arnd@arndb.de, mark.rutland@arm.com
Subject: Re: Need clarity on PCIe MSI interrupt in device tree
Date: Wed, 4 Jan 2017 22:58:59 +0530 [thread overview]
Message-ID: <9f95d60a-6684-3205-eeb0-df86cfe430e4@gmail.com> (raw)
In-Reply-To: <fb1ae45f-1682-c523-ed02-48ca1b890791@arm.com>
Thans Marc
On 1/4/2017 1:59 PM, Marc Zyngier wrote:
> On 04/01/17 03:17, valmiki wrote:
>> Hi,
>>
>> I have confusion on MSI interrupt flags in PCIe documetation.
>>
>> MSI interrupts are edge triggered, but i see some controllers use
>> Ex:tegra <0 99 0x4>, here interrupt flags show 0x4 which means level
>> sensitive as per include/dt-bindings/interrupt-controller/irq.h.
>>
>> May i know why is it like this, why MSI depicted as level sensitive in
>> device tree.
>
> They are not. MSIs are *not* present in the device tree at all.
>
> What you have here is the cascade interrupt from an MSI controller to
> another interrupt controller (probably a GICv2), and that particular
> interrupt is level triggered. Which is perfectly fine if that's the
> signalling method between the two controllers.
>
> This doesn't in any way reflect how MSIs are signalled.
>
> Thanks,
>
> M.
>
next prev parent reply other threads:[~2017-01-04 17:28 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-04 3:17 Need clarity on PCIe MSI interrupt in device tree valmiki
2017-01-04 8:29 ` Marc Zyngier
2017-01-04 17:28 ` valmiki [this message]
2017-01-04 10:05 ` Mark Rutland
2017-01-04 17:29 ` valmiki
2017-01-04 17:39 ` Need clarity on MSI handling in RC driver valmiki
2017-01-04 17:46 ` Marc Zyngier
2017-01-06 2:30 ` valmiki
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