Need clarity on PCIe MSI interrupt in device tree

Need clarity on PCIe MSI interrupt in device tree

[valmiki]

Hi,

I have confusion on MSI interrupt flags in PCIe documetation.

MSI interrupts are edge triggered, but i see some controllers use 
Ex:tegra <0 99 0x4>, here interrupt flags show 0x4 which means level 
sensitive as per include/dt-bindings/interrupt-controller/irq.h.

May i know why is it like this, why MSI depicted as level sensitive in 
device tree.

Regards,
valmiki

Re: Need clarity on PCIe MSI interrupt in device tree

[Marc Zyngier]

On 04/01/17 03:17, valmiki wrote:
> Hi,
> 
> I have confusion on MSI interrupt flags in PCIe documetation.
> 
> MSI interrupts are edge triggered, but i see some controllers use 
> Ex:tegra <0 99 0x4>, here interrupt flags show 0x4 which means level 
> sensitive as per include/dt-bindings/interrupt-controller/irq.h.
> 
> May i know why is it like this, why MSI depicted as level sensitive in 
> device tree.

They are not. MSIs are *not* present in the device tree at all.

What you have here is the cascade interrupt from an MSI controller to
another interrupt controller (probably a GICv2), and that particular
interrupt is level triggered. Which is perfectly fine if that's the
signalling method between the two controllers.

This doesn't in any way reflect how MSIs are signalled.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

Re: Need clarity on PCIe MSI interrupt in device tree

[valmiki]

Thans Marc

On 1/4/2017 1:59 PM, Marc Zyngier wrote:
> On 04/01/17 03:17, valmiki wrote:
>> Hi,
>>
>> I have confusion on MSI interrupt flags in PCIe documetation.
>>
>> MSI interrupts are edge triggered, but i see some controllers use
>> Ex:tegra <0 99 0x4>, here interrupt flags show 0x4 which means level
>> sensitive as per include/dt-bindings/interrupt-controller/irq.h.
>>
>> May i know why is it like this, why MSI depicted as level sensitive in
>> device tree.
>
> They are not. MSIs are *not* present in the device tree at all.
>
> What you have here is the cascade interrupt from an MSI controller to
> another interrupt controller (probably a GICv2), and that particular
> interrupt is level triggered. Which is perfectly fine if that's the
> signalling method between the two controllers.
>
> This doesn't in any way reflect how MSIs are signalled.
>
> Thanks,
>
> 	M.
>

Re: Need clarity on PCIe MSI interrupt in device tree

[Mark Rutland]

On Wed, Jan 04, 2017 at 08:47:43AM +0530, valmiki wrote:
> Hi,

Hi,

> I have confusion on MSI interrupt flags in PCIe documetation.
> 
> MSI interrupts are edge triggered, but i see some controllers use
> Ex:tegra <0 99 0x4>, here interrupt flags show 0x4 which means level
> sensitive as per include/dt-bindings/interrupt-controller/irq.h.

As Marc says, this isn't actually a description of an MSI, but rather
the interrupt generated by the interrupt controller, which is often (but
not always) built into PCIe host controllers.

This looks something like:

+--------+        +-----------------+            +----------+
|        |        +----------+      |~~msi~irq~~>|          |
| Device |==MSI==>| MSI ctrl | PCIe |            | IRQ ctrl |~~~> CPU
|        |        +----------+      |~~intx~irq~>|          |
+--------+        +-----------------+            +----------+

Each PCIe device sends MSIs to the MSI controller. In response to this,
the MSI controller raises a wired interrupt, which is named "msi" in the
DT binding because it is the interrupt generated by the MSI controller,
and the PCIe controller may raise several distinct interrupts which all
need names.

> May i know why is it like this, why MSI depicted as level sensitive
> in device tree.

As above, the interrupt from the MSI controller to the interrupt
controller is level sensitive, but this is not the case for the actual
MSIs.

Thanks,
Mark.

Re: Need clarity on PCIe MSI interrupt in device tree

[valmiki]

Thanks Mark

On 1/4/2017 3:35 PM, Mark Rutland wrote:
> On Wed, Jan 04, 2017 at 08:47:43AM +0530, valmiki wrote:
>> Hi,
>
> Hi,
>
>> I have confusion on MSI interrupt flags in PCIe documetation.
>>
>> MSI interrupts are edge triggered, but i see some controllers use
>> Ex:tegra <0 99 0x4>, here interrupt flags show 0x4 which means level
>> sensitive as per include/dt-bindings/interrupt-controller/irq.h.
>
> As Marc says, this isn't actually a description of an MSI, but rather
> the interrupt generated by the interrupt controller, which is often (but
> not always) built into PCIe host controllers.
>
> This looks something like:
>
> +--------+        +-----------------+            +----------+
> |        |        +----------+      |~~msi~irq~~>|          |
> | Device |==MSI==>| MSI ctrl | PCIe |            | IRQ ctrl |~~~> CPU
> |        |        +----------+      |~~intx~irq~>|          |
> +--------+        +-----------------+            +----------+
>
> Each PCIe device sends MSIs to the MSI controller. In response to this,
> the MSI controller raises a wired interrupt, which is named "msi" in the
> DT binding because it is the interrupt generated by the MSI controller,
> and the PCIe controller may raise several distinct interrupts which all
> need names.
>
>> May i know why is it like this, why MSI depicted as level sensitive
>> in device tree.
>
> As above, the interrupt from the MSI controller to the interrupt
> controller is level sensitive, but this is not the case for the actual
> MSIs.
>
> Thanks,
> Mark.
>

Need clarity on MSI handling in RC driver

[valmiki]

Hi All,

I have a doubt, the MSI domains are handled differently in different RC 
drivers.

Some drivers use irq_domain_add_linear alone, and some use 
pci_msi_create_irq_domain also to handle MSI.

In most of the 32-bit architectures only irq_domain_add_linear is used 
and in 64 bit drivers both pci_msi_create_irq_domain and 
irq_domain_add_linear are used.

So is this because of architecture difference between ARM and ARM64 ?

Thanks & Regards,
valmiki

Re: Need clarity on MSI handling in RC driver

[Marc Zyngier]

On 04/01/17 17:39, valmiki wrote:
> Hi All,
> 
> I have a doubt, the MSI domains are handled differently in different RC 
> drivers.
> 
> Some drivers use irq_domain_add_linear alone, and some use 
> pci_msi_create_irq_domain also to handle MSI.
> 
> In most of the 32-bit architectures only irq_domain_add_linear is used 
> and in 64 bit drivers both pci_msi_create_irq_domain and 
> irq_domain_add_linear are used.
> 
> So is this because of architecture difference between ARM and ARM64 ?

Neither. This is purely a software construct. Newer drivers use the
generic MSI infrastructure (which also allows things like non-PCI MSI),
while older drivers use some ad-hoc infrastructure which is more or less
specific to PCI.

The former is the way to go, and the latter is being phased out.

I'll let Mark draw some shiny ASCII art.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

Re: Need clarity on MSI handling in RC driver

[valmiki]

Thanks Marc

On 1/4/2017 11:16 PM, Marc Zyngier wrote:
> On 04/01/17 17:39, valmiki wrote:
>> Hi All,
>>
>> I have a doubt, the MSI domains are handled differently in different RC
>> drivers.
>>
>> Some drivers use irq_domain_add_linear alone, and some use
>> pci_msi_create_irq_domain also to handle MSI.
>>
>> In most of the 32-bit architectures only irq_domain_add_linear is used
>> and in 64 bit drivers both pci_msi_create_irq_domain and
>> irq_domain_add_linear are used.
>>
>> So is this because of architecture difference between ARM and ARM64 ?
>
> Neither. This is purely a software construct. Newer drivers use the
> generic MSI infrastructure (which also allows things like non-PCI MSI),
> while older drivers use some ad-hoc infrastructure which is more or less
> specific to PCI.
>
> The former is the way to go, and the latter is being phased out.
>
> I'll let Mark draw some shiny ASCII art.
>
> Thanks,
>
> 	M.
>