messages from 2026-08-20 20:06:48 to 2026-08-20 22:11:43 UTC [more...]
[pci:pending/pwrctrl] BUILD SUCCESS 4943d7a5559f0734e5c725c992dfeb02e7306b6a
2026-08-20 22:11 UTC
[pci:controller/tegra264] BUILD SUCCESS 01c3c27a0ef6a7f63559dba33c62377c21fc3ee9
2026-08-20 22:08 UTC
[pci:controller/vmd] BUILD SUCCESS 55aa45154fe48b7d8e96bc031ad27d5b0edfcdb8
2026-08-20 22:09 UTC
[PATCH v5] PCI/pcie: Add PCIe Lane Margining at Receiver (LMR) support
2026-08-20 21:51 UTC (2+ messages)
[PATCH v10 00/12] PCI/CXL: Add CXL reset support for Type 2 devices
2026-08-20 21:13 UTC (3+ messages)
` [PATCH v10 01/12] cxl: Move HDM decoder programming helpers
[PATCH] PCI/sysfs: document the link speed and width attributes
2026-08-20 20:06 UTC (3+ messages)
` [PATCH v2] "
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