From: Jagan Teki <jagannadh.teki@gmail.com>
To: Mohit Kumar <mohit.kumar@st.com>
Cc: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
linux-arm-kernel@lists.infradead.org,
Pratyush Anand <pratyush.anand@st.com>,
Jingoo Han <jg1.han@samsung.com>,
spear-devel <spear-devel@list.st.com>
Subject: Re: [PATCH 07/12] pcie: designware: add dw_pcie prefix before cfg_read/write
Date: Wed, 11 Dec 2013 17:10:08 +0530 [thread overview]
Message-ID: <CAD6G_RTiswApVUz_A3V8A++tQcWaWi2rRtVCuCAFE1eWY6d0CQ@mail.gmail.com> (raw)
In-Reply-To: <11157a3462fcad1067bddd27dcd580bbeb2c289e.1386752447.git.mohit.kumar@st.com>
On Wed, Dec 11, 2013 at 3:08 PM, Mohit Kumar <mohit.kumar@st.com> wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
>
> cfg_read/write function are designware pcie specific. Add dw_pcie prefix
> to avoid collision in global name space.
>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Cc: Mohit Kumar <mohit.kumar@st.com>
> Cc: Jingoo Han <jg1.han@samsung.com>
> Cc: spear-devel@list.st.com
> Cc: linux-pci@vger.kernel.org
> ---
> drivers/pci/host/pci-exynos.c | 5 +++--
> drivers/pci/host/pcie-designware.c | 23 ++++++++++++++---------
> drivers/pci/host/pcie-designware.h | 4 ++--
> 3 files changed, 19 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
> index 24beed3..3de6bfb 100644
> --- a/drivers/pci/host/pci-exynos.c
> +++ b/drivers/pci/host/pci-exynos.c
> @@ -468,7 +468,7 @@ static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
> int ret;
>
> exynos_pcie_sideband_dbi_r_mode(pp, true);
> - ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
> + ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
> exynos_pcie_sideband_dbi_r_mode(pp, false);
> return ret;
> }
> @@ -479,7 +479,8 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
> int ret;
>
> exynos_pcie_sideband_dbi_w_mode(pp, true);
> - ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size, val);
> + ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3),
> + where, size, val);
> exynos_pcie_sideband_dbi_w_mode(pp, false);
> return ret;
> }
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 73aa13c..be6ce30 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -32,7 +32,7 @@ static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
> return sys->private_data;
> }
>
> -int cfg_read(void __iomem *addr, int where, int size, u32 *val)
> +int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
> {
> *val = readl(addr);
>
> @@ -46,7 +46,7 @@ int cfg_read(void __iomem *addr, int where, int size, u32 *val)
> return PCIBIOS_SUCCESSFUL;
> }
>
> -int cfg_write(void __iomem *addr, int where, int size, u32 val)
> +int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
> {
> if (size == 4)
> writel(val, addr);
> @@ -84,7 +84,8 @@ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
> if (pp->ops->rd_own_conf)
> ret = pp->ops->rd_own_conf(pp, where, size, val);
> else
> - ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
> + ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
> + size, val);
>
> return ret;
> }
> @@ -97,8 +98,8 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
> if (pp->ops->wr_own_conf)
> ret = pp->ops->wr_own_conf(pp, where, size, val);
> else
> - ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size,
> - val);
> + ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
> + size, val);
>
> return ret;
> }
> @@ -534,11 +535,13 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>
> if (bus->parent->number == pp->root_bus_nr) {
> dw_pcie_prog_viewport_cfg0(pp, busdev);
> - ret = cfg_read(pp->va_cfg0_base + address, where, size, val);
> + ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
> + val);
> dw_pcie_prog_viewport_mem_outbound(pp);
> } else {
> dw_pcie_prog_viewport_cfg1(pp, busdev);
> - ret = cfg_read(pp->va_cfg1_base + address, where, size, val);
> + ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
> + val);
> dw_pcie_prog_viewport_io_outbound(pp);
> }
>
> @@ -557,11 +560,13 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>
> if (bus->parent->number == pp->root_bus_nr) {
> dw_pcie_prog_viewport_cfg0(pp, busdev);
> - ret = cfg_write(pp->va_cfg0_base + address, where, size, val);
> + ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
> + val);
> dw_pcie_prog_viewport_mem_outbound(pp);
> } else {
> dw_pcie_prog_viewport_cfg1(pp, busdev);
> - ret = cfg_write(pp->va_cfg1_base + address, where, size, val);
> + ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
> + val);
> dw_pcie_prog_viewport_io_outbound(pp);
> }
>
> diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
> index da1ed35..afb1734 100644
> --- a/drivers/pci/host/pcie-designware.h
> +++ b/drivers/pci/host/pcie-designware.h
> @@ -66,8 +66,8 @@ struct pcie_host_ops {
> void (*host_init)(struct pcie_port *pp);
> };
>
> -int cfg_read(void __iomem *addr, int where, int size, u32 *val);
> -int cfg_write(void __iomem *addr, int where, int size, u32 val);
> +int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
> +int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
> void dw_handle_msi_irq(struct pcie_port *pp);
> void dw_pcie_msi_init(struct pcie_port *pp);
> int dw_pcie_link_up(struct pcie_port *pp);
> --
> 1.7.0.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
--
Thanks,
Jagan.
--------
Jagannadha Sutradharudu Teki,
E: jagannadh.teki@gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki
next prev parent reply other threads:[~2013-12-11 11:40 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-11 9:38 [PATCH 00/12] PCI:Add SPEAr13xx PCie support Mohit Kumar
2013-12-11 9:38 ` [PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy-addr Mohit Kumar
2013-12-11 11:09 ` Rajeev kumar
2013-12-11 11:14 ` Rajeev kumar
2013-12-12 0:39 ` Jingoo Han
2013-12-12 3:59 ` Rajeev kumar
2013-12-12 4:07 ` Chen-Yu Tsai
2013-12-12 5:13 ` Mohit KUMAR DCG
2013-12-11 9:38 ` [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header file Mohit Kumar
2013-12-11 22:48 ` Arnd Bergmann
2013-12-13 4:18 ` Mohit KUMAR DCG
2013-12-14 19:02 ` Arnd Bergmann
2014-01-16 7:25 ` Mohit KUMAR DCG
2014-01-16 9:19 ` Pratyush Anand
2014-01-16 11:33 ` Arnd Bergmann
2014-01-16 11:45 ` Pratyush Anand
2013-12-11 9:38 ` [PATCH 03/12] SPEAr13xx: Add SPEAr1310 PCIe register definitions Mohit Kumar
2013-12-11 22:51 ` Arnd Bergmann
2013-12-11 9:38 ` [PATCH 04/12] SPEAr13xx: Fix static mapping table Mohit Kumar
2013-12-11 9:38 ` [PATCH 05/12] clk: SPEAr13xx: Fix pcie clock name Mohit Kumar
2013-12-11 22:42 ` Arnd Bergmann
2013-12-12 5:00 ` Mohit KUMAR DCG
2013-12-12 21:30 ` Arnd Bergmann
2013-12-11 9:38 ` [PATCH 06/12] pcie: designware: Move register definition to the header file Mohit Kumar
2013-12-11 11:38 ` Jagan Teki
2013-12-11 11:55 ` Mohit KUMAR DCG
2013-12-11 12:04 ` Jagan Teki
2013-12-11 21:31 ` Arnd Bergmann
2013-12-11 22:48 ` Jingoo Han
2013-12-12 4:55 ` Mohit KUMAR DCG
2013-12-11 9:38 ` [PATCH 07/12] pcie: designware: add dw_pcie prefix before cfg_read/write Mohit Kumar
2013-12-11 11:40 ` Jagan Teki [this message]
2013-12-12 1:12 ` Jingoo Han
2013-12-12 1:05 ` Jingoo Han
2013-12-20 16:35 ` Bjorn Helgaas
2013-12-11 9:38 ` [PATCH 08/12] pcie: designware: Fix IO transfers Mohit Kumar
2013-12-11 10:03 ` Marek Vasut
2013-12-11 11:29 ` Jagan Teki
2013-12-12 1:17 ` Jingoo Han
2013-12-20 3:47 ` Pratyush Anand
2013-12-11 13:34 ` Arnd Bergmann
2013-12-11 23:34 ` Jingoo Han
2013-12-20 16:36 ` Bjorn Helgaas
2013-12-11 9:38 ` [PATCH 09/12] pcie: SPEAr13xx: Add designware pcie support Mohit Kumar
2013-12-11 23:00 ` Arnd Bergmann
2013-12-13 4:30 ` Mohit KUMAR DCG
2013-12-13 4:57 ` Jingoo Han
2013-12-14 19:01 ` Arnd Bergmann
2013-12-11 9:38 ` [PATCH 10/12] SPEAr13xx: defconfig: Update Mohit Kumar
2013-12-11 10:47 ` Rajeev kumar
2013-12-12 4:47 ` Mohit KUMAR DCG
2013-12-11 9:38 ` [PATCH 11/12] MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer Mohit Kumar
2013-12-12 1:55 ` Jingoo Han
2013-12-11 9:38 ` [PATCH 12/12] MAINTAINERS: Add Synopsis Designware " Mohit Kumar
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