From: Yinghai Lu <yinghai@kernel.org>
To: Johannes Thumshirn <johannes.thumshirn@men.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>
Subject: Re: PCI reset problem
Date: Tue, 3 Sep 2013 12:38:06 -0700 [thread overview]
Message-ID: <CAE9FiQXfJmdNzW3j25qkL4mHWxJQCrp4A+sFOuR63p-OJ72gcQ@mail.gmail.com> (raw)
In-Reply-To: <20130903095500.GA15782@jtlinux>
On Tue, Sep 3, 2013 at 2:55 AM, Johannes Thumshirn
<johannes.thumshirn@men.de> wrote:
>
> As far as I can see with my layman's eyes is, it finds the subordinate busses
> 1-5 behind the bridge but then somehow looses them again in the enumeration
> phase.
fsl-pci fe200000.pcie: PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
pci_bus 0000:00: root bus resource [mem 0x80000000-0x9fffffff]
pci_bus 0000:00: root bus resource [bus 00-ff]
pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to ff
pci_bus 0000:00: scanning bus
pci 0000:00:00.0: [1957:0401] type 01 class 0x0b2000
pci 0000:00:00.0: ignoring class 0x0b2000 (doesn't match header type 01)
pci 0000:00:00.0: calling fixup_hide_host_resource_fsl+0x0/0x6c
calling fixup_hide_host_resource_fsl+
0x0/0x6c @ 1 for 0000:00:00.0
pci fixup fixup_hide_host_resource_fsl+0x0/0x6c returned after 0 usecs
for 0000:00:00.0
pci 0000:00:00.0: calling pcibios_fixup_resources+0x0/0x128
calling pcibios_fixup_resources+0x0/0x128 @ 1 for 0000:00:00.0
pci fixup pcibios_fixup_resources+0x0/0x128 returned after 0 usecs for
0000:00:00.0
pci 0000:00:00.0: calling quirk_fsl_pcie_header+0x0/0x84
calling quirk_fsl_pcie_header+0x0/0x84 @ 1 for 0000:00:00.0
pci fixup quirk_fsl_pcie_header+0x0/0x84 returned after 0 usecs for 0000:00:00.0
===> it overrides the class from 0b2000 to 060400
pci 0000:00:00.0: supports D1 D2
pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
pci 0000:00:00.0: PME# disabled
pci 0000:00:00.0: scanning [bus 01-05] behind bridge, pass 0
pci 0000:00:00.0: check if busn 01-05 is in busn_res: [bus 00-ff]
pci_bus 0000:00: fixups for bus
pci 0000:00:00.0: scanning [bus 00-00] behind bridge, pass 1
====>
so you have PCI_REASSIGN_ALL_BUS set ...
pci_bus 0000:01: busn_res: [bus 01-08] is updated under [bus 00-ff]
pci_bus 0000:01: scanning bus
====> should have child devices probed here... but not happen...
so your pcie switch will need more time to settle down?
pci_bus 0000:01: fixups for bus
pci 0000:00:00.0: PCI bridge to [bus 01-08]
pci 0000:00:00.0: bridge window [io 0x1000-0x1fff]
pci 0000:00:00.0: bridge window [mem 0x80000000-0x801fffff]
pci_bus 0000:01: bus scan returning with max=01
pci_bus 0000:01: busn_res: [bus 01-08] end is updated to 01
pci_bus 0000:00: bus scan returning with max=01
pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 01
next prev parent reply other threads:[~2013-09-03 19:38 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-28 13:33 PCI reset problem Johannes Thumshirn
2013-08-28 16:50 ` Bjorn Helgaas
2013-08-29 8:29 ` Johannes Thumshirn
2013-08-29 12:01 ` Bjorn Helgaas
2013-08-29 15:07 ` Johannes Thumshirn
2013-08-29 15:52 ` Bjorn Helgaas
2013-08-30 8:01 ` Johannes Thumshirn
2013-08-30 13:40 ` Bjorn Helgaas
2013-08-30 13:58 ` Johannes Thumshirn
2013-08-30 19:46 ` Yinghai Lu
2013-09-02 8:00 ` Johannes Thumshirn
2013-09-02 22:18 ` Yinghai Lu
2013-09-03 9:55 ` Johannes Thumshirn
2013-09-03 19:38 ` Yinghai Lu [this message]
2013-09-04 8:10 ` Johannes Thumshirn
2013-08-29 17:40 ` Yinghai Lu
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