From: Bjorn Helgaas <bhelgaas@google.com>
To: Robert Richter <robert.richter@cavium.com>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
Tomasz Nowicki <tn@semihalf.com>,
Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>,
David Daney <ddaney@caviumnetworks.com>,
Vadim.Lomovtsev@caviumnetworks.com,
"Rafael J. Wysocki" <rafael@kernel.org>,
Sunil.Goutham@cavium.com, geethasowjanya.akula@gmail.com,
linu.cherian@cavium.com,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
linux-arm <linux-arm-kernel@lists.infradead.org>,
"linux-acpi@vger.kernel.org" <linux-acpi@vger.kernel.org>
Subject: Re: [PATCH 1/1] PCI: Add MCFG quirk for 2nd node of Cavium ThunderX pass2.x host controller
Date: Mon, 24 Apr 2017 12:05:05 -0500 [thread overview]
Message-ID: <CAErSpo4-a4jKEpxZX3YKeAzE-oVdE3gtRDGSx7nrGuVzK9OKGA@mail.gmail.com> (raw)
In-Reply-To: <20170424093429.GT16981@rric.localdomain>
On Mon, Apr 24, 2017 at 4:34 AM, Robert Richter
<robert.richter@cavium.com> wrote:
> On 21.04.17 11:56:14, Bjorn Helgaas wrote:
>> On Wed, Mar 29, 2017 at 02:16:13PM +0200, Tomasz Nowicki wrote:
>> > Currently SoCs pass2.x do not emulate EA headers for ACPI boot method at all.
>> > However, for pass2.x some devices (like EDAC) advertise incorrect base addresses
>> > in their BARs which results in driver probe failure during resource request.
>> > Since all problematic blocks are on 2nd NUMA node under domain 10 add necessary
>> > quirk entry to obtain BAR addresses correction using EA header emulation.
>> >
>> > Fixes: 44f22bd91e88 ("PCI: Add MCFG quirks for Cavium ThunderX pass2.x host controller")
>> > Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
>> > CC: stable@vger.kernel.org # v4.10+
>>
>> Sorry Tomasz, I must have mistakenly marked this "accepted" in
>> patchwork, so it fell off my to-do list. It's too late to get this in
>> v4.11, but I can still apply it for v4.12.
>>
>> I put it on my pci/host-thunder branch with Robert's ack. I added a preceding
>> patch to tidy up whitespace, which makes this patch look like just:
>>
>> /* SoC pass2.x */
>> THUNDER_PEM_QUIRK(1, 0),
>> THUNDER_PEM_QUIRK(1, 1),
>> + THUNDER_ECAM_QUIRK(1, 10),
>>
>> Please double-check it to make sure this is what you need.
>
> Bjorn,
>
> since the second is marked stable there will be conflicts when
> applying it to stable (or built errors). The best would be to change
> order of both (128cd6e8249f^, 128cd6e8249f) for smooth backporting
> which makes it then more close to Tomasz's version again.
Thanks, I should have noticed that. Could go either way; I just
marked 128cd6e8249f^ for stable as well, since it seemed marginally
easier to read to split the whitespace changes from the real change.
>> > ---
>> > drivers/acpi/pci_mcfg.c | 7 ++++---
>> > 1 file changed, 4 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
>> > index a6a4cea..a0a391e 100644
>> > --- a/drivers/acpi/pci_mcfg.c
>> > +++ b/drivers/acpi/pci_mcfg.c
>> > @@ -90,13 +90,14 @@ static struct mcfg_fixup mcfg_quirks[] = {
>> > &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) }, \
>> > { "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \
>> > &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) }
>> > +#define THUNDER_ECAM_QUIRK(rev, seg) \
>> > + { "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY, \
>> > + &pci_thunder_ecam_ops }
>> > /* SoC pass2.x */
>> > THUNDER_PEM_QUIRK(1, 0),
>> > THUNDER_PEM_QUIRK(1, 1),
>> > + THUNDER_ECAM_QUIRK(1, 10),
>> >
>> > -#define THUNDER_ECAM_QUIRK(rev, seg) \
>> > - { "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY, \
>> > - &pci_thunder_ecam_ops }
>> > /* SoC pass1.x */
>> > THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */
>> > THUNDER_PEM_QUIRK(2, 1), /* off-chip devices */
>> > --
>> > 2.7.4
>> >
> --
> To unsubscribe from this list: send the line "unsubscribe linux-acpi" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
prev parent reply other threads:[~2017-04-24 17:05 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-29 12:16 [PATCH 1/1] PCI: Add MCFG quirk for 2nd node of Cavium ThunderX pass2.x host controller Tomasz Nowicki
2017-04-21 11:34 ` Robert Richter
2017-04-21 16:56 ` Bjorn Helgaas
2017-04-21 17:30 ` Tomasz Nowicki
2017-04-24 9:34 ` Robert Richter
2017-04-24 17:05 ` Bjorn Helgaas [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAErSpo4-a4jKEpxZX3YKeAzE-oVdE3gtRDGSx7nrGuVzK9OKGA@mail.gmail.com \
--to=bhelgaas@google.com \
--cc=Lorenzo.Pieralisi@arm.com \
--cc=Sunil.Goutham@cavium.com \
--cc=Vadim.Lomovtsev@caviumnetworks.com \
--cc=ddaney@caviumnetworks.com \
--cc=geethasowjanya.akula@gmail.com \
--cc=helgaas@kernel.org \
--cc=linu.cherian@cavium.com \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-pci@vger.kernel.org \
--cc=rafael@kernel.org \
--cc=robert.richter@cavium.com \
--cc=tn@semihalf.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).